Messages in this thread | | | Date | Wed, 20 Jul 2022 00:06:30 +0200 | From | Michael Grzeschik <> | Subject | Re: [PATCH 0/2] usb: dwc3: core: Enable GUCTL1 bit 10 for fixing crc error after resume |
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Hi Piyush!
On Mon, Jun 13, 2022 at 06:17:01PM +0530, Piyush Mehta wrote: >This patch of the series does the following: >- Add a new DT "snps,enable_guctl1_resume_quirk" quirk >- Enable GUCTL1 bit 10 for fixing crc error after resume bug > When this bit is set to '1', the ULPI opmode will be changed > to 'normal' along with HS terminations after EOR. > This option is to support certain legacy ULPI PHYs. > >Piyush Mehta (2): > dt-bindings: usb: snps,dwc3: Add 'snps,enable_guctl1_resume_quirk' > quirk > usb: dwc3: core: Enable GUCTL1 bit 10 for fixing crc error after > resume bug > > .../devicetree/bindings/usb/snps,dwc3.yaml | 6 ++++++ > drivers/usb/dwc3/core.c | 16 ++++++++++++++++ > drivers/usb/dwc3/core.h | 6 ++++++ > 3 files changed, 28 insertions(+)
I found your series and am wondering if you are planning to send a v2 of it? It would really help to see this mainline.
The Xilinx Register Reference states BIT 10 as
RESUME_TERMSEL_XCVRSEL_UNIFY
which seems to be more meaningful than GUCTL1_RESUME_QUIRK. It would probably make sense to work this in for v2.
The Documentation is also refering more than just opmode to be 0 during EOR. (termsel, xcvrsel, opmode).
https://www.xilinx.com/htmldocs/registers/ug1087/ug1087-zynq-ultrascale-registers.html#usb3_xhci___guctl1.html
Regards, Michael
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