Messages in this thread | | | Date | Tue, 19 Jul 2022 17:38:20 +0100 | From | Jonathan Cameron <> | Subject | Re: [PATCH V14 4/7] cxl/pci: Create PCI DOE mailbox's for memory devices |
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On Thu, 14 Jul 2022 20:04:21 -0700 ira.weiny@intel.com wrote:
> From: Ira Weiny <ira.weiny@intel.com> > > DOE mailbox objects will be needed for various mailbox communications > with each memory device. > > Iterate each DOE mailbox capability and create PCI DOE mailbox objects > as found. > > It is not anticipated that this is the final resting place for the > iteration of the DOE devices. The support of switch ports will drive > this code into the PCIe side. In this imagined architecture the CXL > port driver would then query into the PCI device for the DOE mailbox > array. > > For now creating the mailboxes in the CXL port is good enough for the > endpoints. Later PCIe ports will need to support this to support switch > ports more generically. > > Cc: Dan Williams <dan.j.williams@intel.com> > Cc: Davidlohr Bueso <dave@stgolabs.net> > Cc: Lukas Wunner <lukas@wunner.de> > Signed-off-by: Ira Weiny <ira.weiny@intel.com> LGTM
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
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