lkml.org 
[lkml]   [2022]   [Jul]   [18]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    /
    Date
    From
    SubjectRe: [PATCH v2 2/6] PCI: brcmstb: Split brcm_pcie_setup() into two funcs
    On Monday 18 July 2022 12:05:28 Bjorn Helgaas wrote:
    > On Mon, Jul 18, 2022 at 09:37:08AM -0400, Jim Quinlan wrote:
    > > On Mon, Jul 18, 2022 at 9:11 AM Pali Rohár <pali@kernel.org> wrote:
    > > >
    > > > Hello!
    > > >
    > > > On Saturday 16 July 2022 18:24:49 Jim Quinlan wrote:
    > > > > @@ -948,6 +941,40 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
    > > > > if (pcie->gen)
    > > > > brcm_pcie_set_gen(pcie, pcie->gen);
    > > > >
    > > > > + /* Don't advertise L0s capability if 'aspm-no-l0s' */
    > > > > + aspm_support = PCIE_LINK_STATE_L1;
    > > > > + if (!of_property_read_bool(pcie->np, "aspm-no-l0s"))
    > > > > + aspm_support |= PCIE_LINK_STATE_L0S;
    > > > > + tmp = readl(base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY);
    > > > > + u32p_replace_bits(&tmp, aspm_support,
    > > > > + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK);
    > > > > + writel(tmp, base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY);
    > > > > +
    > > > > + /*
    > > > > + * For config space accesses on the RC, show the right class for
    > > > > + * a PCIe-PCIe bridge (the default setting is to be EP mode).
    > > > > + */
    > > > > + tmp = readl(base + PCIE_RC_CFG_PRIV1_ID_VAL3);
    > > > > + u32p_replace_bits(&tmp, 0x060400,
    > > >
    > > > There is already macro PCI_CLASS_BRIDGE_PCI_NORMAL, so please use it
    > > > instead of magic constant.
    > >
    > > Will do, thanks.
    >
    > I can fix that up locally.

    Great!

    I did git grep on recent master branch and found another candidates with
    magic numbers which refers to PCI_CLASS_BRIDGE_PCI_NORMAL:

    arch/mips/pci/pci-mt7620.c: pcie_w32(0x06040001, RALINK_PCI0_CLASS);
    arch/mips/pci/pci-rt3883.c: rt3883_pci_w32(rpc, 0x06040001, RT3883_PCI_REG_CLASS(1));
    arch/powerpc/platforms/4xx/pci.c: out_le32(mbase + 0x208, 0x06040001);
    drivers/pci/controller/pcie-brcmstb.c: u32p_replace_bits(&tmp, 0x060400,

    (class code is stored in upper 24 bits of 32-bit register, so it makes
    sense that on lowest 8 bits is something more - 0x01)

    What do you think? Does it make sense to send patch which replace above
    hex numbers by macros?

    > > > I introduced it recently in commit:
    > > > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=904b10fb189cc15376e9bfce1ef0282e68b0b004
    > > >
    > > > > + PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK);
    > > > > + writel(tmp, base + PCIE_RC_CFG_PRIV1_ID_VAL3);
    > > > > +
    > > > > + return 0;
    > > > > +}
    >
    >
    >
    > > _______________________________________________
    > > linux-arm-kernel mailing list
    > > linux-arm-kernel@lists.infradead.org
    > > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
    >

    \
     
     \ /
      Last update: 2022-07-18 20:02    [W:5.489 / U:0.764 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site