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SubjectRe: [PATCH v2 2/6] PCI: brcmstb: Split brcm_pcie_setup() into two funcs
Hello!

On Saturday 16 July 2022 18:24:49 Jim Quinlan wrote:
> @@ -948,6 +941,40 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
> if (pcie->gen)
> brcm_pcie_set_gen(pcie, pcie->gen);
>
> + /* Don't advertise L0s capability if 'aspm-no-l0s' */
> + aspm_support = PCIE_LINK_STATE_L1;
> + if (!of_property_read_bool(pcie->np, "aspm-no-l0s"))
> + aspm_support |= PCIE_LINK_STATE_L0S;
> + tmp = readl(base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY);
> + u32p_replace_bits(&tmp, aspm_support,
> + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK);
> + writel(tmp, base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY);
> +
> + /*
> + * For config space accesses on the RC, show the right class for
> + * a PCIe-PCIe bridge (the default setting is to be EP mode).
> + */
> + tmp = readl(base + PCIE_RC_CFG_PRIV1_ID_VAL3);
> + u32p_replace_bits(&tmp, 0x060400,

There is already macro PCI_CLASS_BRIDGE_PCI_NORMAL, so please use it
instead of magic constant.

I introduced it recently in commit:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=904b10fb189cc15376e9bfce1ef0282e68b0b004

> + PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK);
> + writel(tmp, base + PCIE_RC_CFG_PRIV1_ID_VAL3);
> +
> + return 0;
> +}

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