lkml.org 
[lkml]   [2022]   [Jul]   [18]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    /
    From
    Date
    SubjectRe: [patch 00/38] x86/retbleed: Call depth tracking mitigation
    On Mon, Jul 18, 2022 at 3:59 PM Thomas Gleixner <tglx@linutronix.de> wrote:
    >
    > That's bad. The function entry should be 16 byte aligned and as I just
    > learned for AMD the ideal alignment would be possibly 32 byte as that's
    > their I-fetch width.

    In general, the L1 cache line size is likely the only "ideal" alignment.

    Even if (I think) intel fetches just 16 bytes per cycle from the L1 I$
    when decoding, being cacheline aligned still means that the L2->L1
    transfer for the beginning of the function starts out better.

    But Intel's current optimization many actually end sup having special rules:

    When executing code from the Decoded Icache, direct branches that
    are mostly taken should have all their instruction bytes in a 64B
    cache line and nearer the end of that cache line. Their targets should
    be at or near the beginning of a 64B cache line.

    When executing code from the legacy decode pipeline, direct
    branches that are mostly taken should have all their instruction bytes
    in a 16B aligned chunk of memory and nearer the end of that 16B
    aligned chunk. Their targets should be at or near the beginning of a
    16B aligned chunk of memory.

    So note how the branch itself should be at the end of the chunk, but
    the branch _target_ should be at the beginning of the chunk. And the
    chunk size is 16 bytes for decoding new instructions, and 64 bytes for
    predecoded.

    I suspect that for the kernel, and for the beginning of the function
    (ie the target case), the 16-byte thing is still the main thing.
    Because the L0 I$ ("uop cache", "Decoded Icache", whatever you want to
    call it) is probably too small for a lot of kernel loads where user
    space has flushed things in between system calls or faults.

    Older versions of the intel code just said "All branch targets should
    be 16-byte aligned".

    So I think 16 bytes for function alignment ends up being what we
    generally want, but yes, it's slowly changing. AMD fetches 32-byte
    chunks, and Intel has that 64-bit predecode thing.

    Linus

    \
     
     \ /
      Last update: 2022-07-19 01:45    [W:5.090 / U:0.216 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site