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SubjectRe: [PATCH v2] PCI: qcom: Allow L1 and its sub states
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On 7/15/2022 1:54 PM, Manivannan Sadhasivam wrote:
> On Wed, Jun 15, 2022 at 06:45:39PM +0530, Krishna chaitanya chundru wrote:
>> Allow L1 and its sub-states in the qcom pcie driver.
>> By default this is disabled in the hardware. So enabling it explicitly.
>>
> You are enabling L1ss for controllers belonging to 2_7_0, so this should
> be mentioned in the commit message. Otherwise, it will imply that the
> L1ss is added for all controller versions.
>
>> Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
>> ---
> Change log should be added here for versions > 1.
>
> Thanks,
> Mani

I will update new patch with your inputs.


Thanks,

Krishna Chaitanya.

>
>> drivers/pci/controller/dwc/pcie-qcom.c | 8 ++++++++
>> 1 file changed, 8 insertions(+)
>>
>> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
>> index 6ab9089..0d8efcc 100644
>> --- a/drivers/pci/controller/dwc/pcie-qcom.c
>> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
>> @@ -41,6 +41,9 @@
>> #define L23_CLK_RMV_DIS BIT(2)
>> #define L1_CLK_RMV_DIS BIT(1)
>>
>> +#define PCIE20_PARF_PM_CTRL 0x20
>> +#define REQ_NOT_ENTR_L1 BIT(5)
>> +
>> #define PCIE20_PARF_PHY_CTRL 0x40
>> #define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK GENMASK(20, 16)
>> #define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) ((x) << 16)
>> @@ -1267,6 +1270,11 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
>> val |= BIT(4);
>> writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
>>
>> + /* Enable L1 and L1ss */
>> + val = readl(pcie->parf + PCIE20_PARF_PM_CTRL);
>> + val &= ~REQ_NOT_ENTR_L1;
>> + writel(val, pcie->parf + PCIE20_PARF_PM_CTRL);
>> +
>> if (IS_ENABLED(CONFIG_PCI_MSI)) {
>> val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
>> val |= BIT(31);
>> --
>> 2.7.4
>>

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