Messages in this thread Patch in this message | | | From | Perry Yuan <> | Subject | [PATCH v4 04/13] cpufreq: amd-pstate: prefetch cppc_req_cached value in amd_pstate_cpu_init() | Date | Fri, 15 Jul 2022 06:04:23 -0400 |
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This cppc_req_cached valued should be prefetched during amd_pstate_cpu_init call period, then the amd_pstate_update() will get correct cached value before updating the perf to change the cpu perf level.The cached values are read through MSR interface, so here use shared_mem flag to check the registers are accessible
Also the core performance boost state will be initialized through hardware configuration register
* shared_mem flag is used for the shared memory type CPPC implementation which dose not support MSR interface operation
Signed-off-by: Perry Yuan <Perry.Yuan@amd.com> --- drivers/cpufreq/amd-pstate.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 43e6df9f67f6..d8c4153dbe4f 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -92,6 +92,8 @@ struct amd_aperf_mperf { * @prev: Last Aperf/Mperf/tsc count value read from register * @freq: current cpu frequency value * @boost_supported: check whether the Processor or SBIOS supports boost mode + * @precision_boost_off: the core performance boost disabled state + * @cppc_hw_conf_cached: the cached hardware configuration register * * The amd_cpudata is key private data for each CPU thread in AMD P-State, and * represents all the attributes and goals that AMD P-State requests at runtime. @@ -117,6 +119,7 @@ struct amd_cpudata { u64 freq; bool boost_supported; + bool precision_boost_off; u64 cppc_hw_conf_cached; }; @@ -547,12 +550,17 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy) cpudata->lowest_nonlinear_freq = lowest_nonlinear_freq; policy->driver_data = cpudata; + if (!shared_mem) { + ret = rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_HW_CTL, &value); + if (ret) + return ret; + cpudata->precision_boost_off = value & AMD_CPPC_PRECISION_BOOST_ENABLED; - ret = rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_HW_CTL, &value); - if (ret) - return ret; - WRITE_ONCE(cpudata->cppc_hw_conf_cached, value); - + ret = rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, &value); + if (ret) + return ret; + WRITE_ONCE(cpudata->cppc_req_cached, value); + } amd_pstate_boost_init(cpudata); return 0; -- 2.32.0
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