Messages in this thread | | | Date | Thu, 14 Jul 2022 18:35:17 +0530 | Subject | Re: [V5] tty: serial: qcom-geni-serial: Fix get_clk_div_rate() which otherwise could return a sub-optimal clock rate. | From | Vijaya Krishna Nivarthi <> |
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On 7/14/2022 4:16 PM, Jiri Slaby wrote: > On 12. 07. 22, 14:45, Vijaya Krishna Nivarthi wrote: > ... >> +static unsigned long get_clk_div_rate(struct clk *clk, struct device >> *dev, >> + unsigned int baud, unsigned int sampling_rate, unsigned int >> *clk_div) >> +{ >> + unsigned long ser_clk; >> + unsigned long desired_clk; >> + >> + desired_clk = baud * sampling_rate; >> + if (!desired_clk) { >> + dev_dbg(dev, "Invalid frequency\n"); >> + return 0; >> } >> - *clk_div = ser_clk / desired_clk; >> - if (!(*clk_div)) >> - *clk_div = 1; >> + /* >> + * try to find a clock rate within 2% tolerance, then within > > "then within" ... "5" is missing, perhaps?
Yes :(
Will change.
> >> + */ >> + ser_clk = find_clk_rate_in_tol(clk, desired_clk, clk_div, 2); >> + if (!ser_clk) >> + ser_clk = find_clk_rate_in_tol(clk, desired_clk, clk_div, 5); >> + >> + if (!ser_clk) >> + dev_err(dev, "Couldn't find suitable clock rate for %lu\n", >> desired_clk); >> + else >> + dev_dbg(dev, "desired_clk-%lu, ser_clk-%lu, clk_div-%u\n", >> + desired_clk, ser_clk, *clk_div); >> return ser_clk; >> } >> @@ -1021,8 +1040,8 @@ static void qcom_geni_serial_set_termios(struct >> uart_port *uport, >> if (ver >= QUP_SE_VERSION_2_5) >> sampling_rate /= 2; >> - clk_rate = get_clk_div_rate(port->se.clk, baud, >> - sampling_rate, &clk_div); >> + clk_rate = get_clk_div_rate(port->se.clk, port->se.dev, baud, > > Maybe worth passing whole geni_se (port->se) then?
but then geni_se is a struct; shall we pass port instead?
Alternately move logging to caller?
Thank you.
> >> + sampling_rate, &clk_div); >> if (!clk_rate) >> goto out_restart_rx; > > thanks,
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