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    SubjectRe: [PATCH v1 2/2] riscv: dts: starfive: add the missing monitor core
    Date
    On 13/07/2022 16:15, Icenowy Zheng wrote:
    > 在 2022-07-11星期一的 19:43 +0100,Conor Dooley写道:
    >> From: Conor Dooley <conor.dooley@microchip.com>
    >>
    >> The JH7100 has a 32 bit monitor core that is missing from the device
    >> tree. Add it (and its cpu-map entry) to more accurately reflect the
    >> actual topology of the SoC.
    >>
    >> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
    >> ---
    >>  arch/riscv/boot/dts/starfive/jh7100.dtsi | 21 +++++++++++++++++++++
    >>  1 file changed, 21 insertions(+)
    >>
    >> diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi
    >> b/arch/riscv/boot/dts/starfive/jh7100.dtsi
    >> index c617a61e26e2..92fce5b66d3d 100644
    >> --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
    >> +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
    >> @@ -67,6 +67,23 @@ cpu1_intc: interrupt-controller {
    >>                         };
    >>                 };
    >>  
    >> +               E24: cpu@2 {
    >> +                       compatible = "sifive,e24", "riscv";
    >
    > Oh, by the way "sifive,e24" is not a documented compatible in the DT
    > binding.
    >
    > If you really want to add it here, you need to add the compatible
    > string to the DT binding first.

    Check patch 1/2.

    >
    >> +                       reg = <2>;
    >> +                       device_type = "cpu";
    >> +                       i-cache-block-size = <32>;
    >> +                       i-cache-sets = <256>;
    >> +                       i-cache-size = <16384>;
    >> +                       riscv,isa = "rv32imafc";
    >> +                       status = "disabled";
    >> +
    >> +                       cpu2_intc: interrupt-controller {
    >> +                               compatible = "riscv,cpu-intc";
    >> +                               interrupt-controller;
    >> +                               #interrupt-cells = <1>;
    >> +                       };
    >> +               };
    >> +
    >>                 cpu-map {
    >>                         cluster0 {
    >>                                 core0 {
    >> @@ -76,6 +93,10 @@ core0 {
    >>                                 core1 {
    >>                                         cpu = <&U74_1>;
    >>                                 };
    >> +
    >> +                               core2 {
    >> +                                       cpu = <&E24>;
    >> +                               };
    >>                         };
    >>                 };
    >>         };
    >
    >
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