Messages in this thread | | | Date | Wed, 13 Jul 2022 16:07:39 +0100 | From | Paul Cercueil <> | Subject | Re: [PATCH v4 07/11] ASoC: jz4740-i2s: Make the PLL clock name SoC-specific |
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Hi Zhou,
Le mer., juil. 13 2022 at 22:33:44 +0800, Zhou Yanjie <zhouyu@wanyeetech.com> a écrit : > Hi Aidan, > > On 2022/7/9 上午12:02, Aidan MacDonald wrote: >> On some Ingenic SoCs, such as the X1000, there is a programmable >> divider used to generate the I2S system clock from a PLL, rather >> than a fixed PLL/2 clock. It doesn't make much sense to call the >> clock "pll half" on those SoCs, so the clock name should really be >> a SoC-dependent value. >> >> Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com> >> --- >> sound/soc/jz4740/jz4740-i2s.c | 8 +++++++- >> 1 file changed, 7 insertions(+), 1 deletion(-) >> >> diff --git a/sound/soc/jz4740/jz4740-i2s.c >> b/sound/soc/jz4740/jz4740-i2s.c >> index 0dcc658b3784..a41398c24d0e 100644 >> --- a/sound/soc/jz4740/jz4740-i2s.c >> +++ b/sound/soc/jz4740/jz4740-i2s.c >> @@ -75,6 +75,8 @@ struct i2s_soc_info { >> struct reg_field field_i2sdiv_capture; >> struct reg_field field_i2sdiv_playback; >> + const char *pll_clk_name; >> + >> bool shared_fifo_flush; >> }; >> @@ -281,7 +283,7 @@ static int jz4740_i2s_set_sysclk(struct >> snd_soc_dai *dai, int clk_id, >> clk_set_parent(i2s->clk_i2s, parent); >> break; >> case JZ4740_I2S_CLKSRC_PLL: >> - parent = clk_get(NULL, "pll half"); >> + parent = clk_get(NULL, i2s->soc_info->pll_clk_name); >> if (IS_ERR(parent)) >> return PTR_ERR(parent); >> clk_set_parent(i2s->clk_i2s, parent); >> @@ -400,6 +402,7 @@ static const struct i2s_soc_info >> jz4740_i2s_soc_info = { >> .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 8, 11), >> .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), >> .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), >> + .pll_clk_name = "pll half", >> .shared_fifo_flush = true, >> }; >> @@ -409,6 +412,7 @@ static const struct i2s_soc_info >> jz4760_i2s_soc_info = { >> .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 16, 20), >> .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), >> .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), >> + .pll_clk_name = "pll half", >> }; > > > Since JZ4760, according to the description of the I2SCDR register, > Ingenic SoCs no longer use PLL/2 clock, but directly use PLL clock, > so it seems also inappropriate to use "pll half" for these SoCs.
The device tree passes the clock as "pll half". So the driver should use this name as well...
Cheers, -Paul
>> static struct snd_soc_dai_driver jz4770_i2s_dai = { >> @@ -435,6 +439,7 @@ static const struct i2s_soc_info >> jz4770_i2s_soc_info = { >> .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 16, 20), >> .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 8, 11), >> .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), >> + .pll_clk_name = "pll half", >> }; > > > Same here. > > >> static const struct i2s_soc_info jz4780_i2s_soc_info = { >> @@ -443,6 +448,7 @@ static const struct i2s_soc_info >> jz4780_i2s_soc_info = { >> .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 16, 20), >> .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 8, 11), >> .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), >> + .pll_clk_name = "pll half", >> }; >> > > Same here. > > > Thanks and best regards! > > >> static const struct snd_soc_component_driver jz4740_i2s_component >> = {
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