Messages in this thread Patch in this message | | | From | Like Xu <> | Subject | [PATCH 1/7] perf/x86/core: Update x86_pmu.pebs_capable for ICELAKE_{X,D} | Date | Wed, 13 Jul 2022 20:25:00 +0800 |
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From: Like Xu <likexu@tencent.com>
Ice Lake microarchitecture with EPT-Friendly PEBS capability also support the Extended feature, which means that all counters (both fixed function and general purpose counters) can be used for PEBS events.
Update x86_pmu.pebs_capable like SPR to apply PEBS_ALL semantics.
Cc: Kan Liang <kan.liang@linux.intel.com> Fixes: fb358e0b811e ("perf/x86/intel: Add EPT-Friendly PEBS for Ice Lake Server") Signed-off-by: Like Xu <likexu@tencent.com> --- arch/x86/events/intel/core.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 4e9b7af9cc45..e46fd496187b 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -6239,6 +6239,7 @@ __init int intel_pmu_init(void) case INTEL_FAM6_ICELAKE_X: case INTEL_FAM6_ICELAKE_D: x86_pmu.pebs_ept = 1; + x86_pmu.pebs_capable = ~0ULL; pmem = true; fallthrough; case INTEL_FAM6_ICELAKE_L: -- 2.37.0
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