lkml.org 
[lkml]   [2022]   [Jul]   [13]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    /
    SubjectRe: [PATCH v14 05/10] drm/mediatek: Add MT8195 Embedded DisplayPort driver
    From
    Date
    Hi, Bo-Chen:

    On Tue, 2022-07-12 at 19:12 +0800, Bo-Chen Chen wrote:
    > From: Markus Schneider-Pargmann <msp@baylibre.com>
    >
    > This patch adds a embedded displayport driver for the MediaTek mt8195
    > SoC.
    >
    > It supports the MT8195, the embedded DisplayPort units. It offers
    > DisplayPort 1.4 with up to 4 lanes.
    >
    > The driver creates a child device for the phy. The child device will
    > never exist without the parent being active. As they are sharing a
    > register range, the parent passes a regmap pointer to the child so
    > that
    > both can work with the same register range. The phy driver sets
    > device
    > data that is read by the parent to get the phy device that can be
    > used
    > to control the phy properties.
    >
    > This driver is based on an initial version by
    > Jitao shi <jitao.shi@mediatek.com>
    >
    > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
    > Signed-off-by: Guillaume Ranquet <granquet@baylibre.com>
    > Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
    > ---

    [snip]

    > +
    > +static void mtk_dp_set_msa(struct mtk_dp *mtk_dp)
    > +{
    > + struct drm_display_mode mode;
    > + struct mtk_dp_timings *timings = &mtk_dp->info.timings;
    > +
    > + drm_display_mode_from_videomode(&timings->vm, &mode);
    > +
    > + /* horizontal */
    > + mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3010,
    > + mode.htotal, HTOTAL_SW_DP_ENC0_P0_MASK);
    > + mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3018,
    > + timings->vm.hsync_len + timings-
    > >vm.hback_porch,
    > + HSTART_SW_DP_ENC0_P0_MASK);
    > + mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3028,
    > + timings->vm.hsync_len <<
    > HSW_SW_DP_ENC0_P0_SHIFT,

    Directly use a number for shift because we know it's a shift, so it's
    not necessary to define a symbol for shift.

    > + HSW_SW_DP_ENC0_P0_MASK);
    > + mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3028,
    > + 0, HSP_SW_DP_ENC0_P0_MASK);
    > + mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3020,
    > + timings->vm.hactive,
    > HWIDTH_SW_DP_ENC0_P0_MASK);
    > +
    > + /* vertical */
    > + mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3014,
    > + mode.vtotal, VTOTAL_SW_DP_ENC0_P0_MASK);
    > + mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_301C,
    > + timings->vm.vsync_len + timings-
    > >vm.vback_porch,
    > + VSTART_SW_DP_ENC0_P0_MASK);
    > + mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_302C,
    > + timings->vm.vsync_len <<
    > VSW_SW_DP_ENC0_P0_SHIFT,

    Ditto.

    Regards,
    CK

    > + VSW_SW_DP_ENC0_P0_MASK);
    > + mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_302C,
    > + 0, VSP_SW_DP_ENC0_P0_MASK);
    > + mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3024,
    > + timings->vm.vactive,
    > VHEIGHT_SW_DP_ENC0_P0_MASK);
    > +
    > + /* horizontal */
    > + mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3064,
    > + timings->vm.hactive,
    > HDE_NUM_LAST_DP_ENC0_P0_MASK);
    > + mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3154,
    > + mode.htotal, PGEN_HTOTAL_DP_ENC0_P0_MASK);
    > + mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3158,
    > + timings->vm.hfront_porch,
    > + PGEN_HSYNC_RISING_DP_ENC0_P0_MASK);
    > + mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_315C,
    > + timings->vm.hsync_len,
    > + PGEN_HSYNC_PULSE_WIDTH_DP_ENC0_P0_MASK);
    > + mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3160,
    > + timings->vm.hback_porch + timings-
    > >vm.hsync_len,
    > + PGEN_HFDE_START_DP_ENC0_P0_MASK);
    > + mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3164,
    > + timings->vm.hactive,
    > + PGEN_HFDE_ACTIVE_WIDTH_DP_ENC0_P0_MASK);
    > +
    > + /* vertical */
    > + mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3168,
    > + mode.vtotal,
    > + PGEN_VTOTAL_DP_ENC0_P0_MASK);
    > + mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_316C,
    > + timings->vm.vfront_porch,
    > + PGEN_VSYNC_RISING_DP_ENC0_P0_MASK);
    > + mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3170,
    > + timings->vm.vsync_len,
    > + PGEN_VSYNC_PULSE_WIDTH_DP_ENC0_P0_MASK);
    > + mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3174,
    > + timings->vm.vback_porch + timings-
    > >vm.vsync_len,
    > + PGEN_VFDE_START_DP_ENC0_P0_MASK);
    > + mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3178,
    > + timings->vm.vactive,
    > + PGEN_VFDE_ACTIVE_WIDTH_DP_ENC0_P0_MASK);
    > +}
    > +

    \
     
     \ /
      Last update: 2022-07-13 11:47    [W:3.122 / U:0.032 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site