Messages in this thread | | | Subject | Re: [PATCH v14 05/10] drm/mediatek: Add MT8195 Embedded DisplayPort driver | From | CK Hu <> | Date | Wed, 13 Jul 2022 17:12:35 +0800 |
| |
Hi, Bo-Chen:
On Tue, 2022-07-12 at 19:12 +0800, Bo-Chen Chen wrote: > From: Markus Schneider-Pargmann <msp@baylibre.com> > > This patch adds a embedded displayport driver for the MediaTek mt8195 > SoC. > > It supports the MT8195, the embedded DisplayPort units. It offers > DisplayPort 1.4 with up to 4 lanes. > > The driver creates a child device for the phy. The child device will > never exist without the parent being active. As they are sharing a > register range, the parent passes a regmap pointer to the child so > that > both can work with the same register range. The phy driver sets > device > data that is read by the parent to get the phy device that can be > used > to control the phy properties. > > This driver is based on an initial version by > Jitao shi <jitao.shi@mediatek.com> > > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> > Signed-off-by: Guillaume Ranquet <granquet@baylibre.com> > Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> > ---
[snip]
> + > +static void mtk_dp_msa_bypass_enable(struct mtk_dp *mtk_dp, bool > enable) > +{ > + u32 mask = BIT(HTOTAL_SEL_DP_ENC0_P0_SHIFT) | > + BIT(VTOTAL_SEL_DP_ENC0_P0_SHIFT) | > + BIT(HSTART_SEL_DP_ENC0_P0_SHIFT) | > + BIT(VSTART_SEL_DP_ENC0_P0_SHIFT) | > + BIT(HWIDTH_SEL_DP_ENC0_P0_SHIFT) | > + BIT(VHEIGHT_SEL_DP_ENC0_P0_SHIFT) | > + BIT(HSP_SEL_DP_ENC0_P0_SHIFT) | > + BIT(HSW_SEL_DP_ENC0_P0_SHIFT) | > + BIT(VSP_SEL_DP_ENC0_P0_SHIFT) | > + BIT(VSW_SEL_DP_ENC0_P0_SHIFT);
I would like define a symbol like this
#define HTOTAL_SEL_DP_ENC0_P0 BIT(0) #define VTOTAL_SEL_DP_ENC0_P0 BIT(1) #define HSTART_SEL_DP_ENC0_P0 BIT(2)
Regards, CK
> + u32 val = enable ? 0 : mask; > + > + mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3030, val, mask); > +} > +
| |