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    Subject[PATCH 5.15 47/78] x86/bugs: Optimize SPEC_CTRL MSR writes
    Date
    From: Peter Zijlstra <peterz@infradead.org>

    commit c779bc1a9002fa474175b80e72b85c9bf628abb0 upstream.

    When changing SPEC_CTRL for user control, the WRMSR can be delayed
    until return-to-user when KERNEL_IBRS has been enabled.

    This avoids an MSR write during context switch.

    Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
    Signed-off-by: Borislav Petkov <bp@suse.de>
    Reviewed-by: Josh Poimboeuf <jpoimboe@kernel.org>
    Signed-off-by: Borislav Petkov <bp@suse.de>
    Signed-off-by: Thadeu Lima de Souza Cascardo <cascardo@canonical.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
    ---
    arch/x86/include/asm/nospec-branch.h | 2 +-
    arch/x86/kernel/cpu/bugs.c | 18 ++++++++++++------
    arch/x86/kernel/process.c | 2 +-
    3 files changed, 14 insertions(+), 8 deletions(-)

    --- a/arch/x86/include/asm/nospec-branch.h
    +++ b/arch/x86/include/asm/nospec-branch.h
    @@ -254,7 +254,7 @@ static inline void indirect_branch_predi

    /* The Intel SPEC CTRL MSR base value cache */
    extern u64 x86_spec_ctrl_base;
    -extern void write_spec_ctrl_current(u64 val);
    +extern void write_spec_ctrl_current(u64 val, bool force);

    /*
    * With retpoline, we must use IBRS to restrict branch prediction
    --- a/arch/x86/kernel/cpu/bugs.c
    +++ b/arch/x86/kernel/cpu/bugs.c
    @@ -63,13 +63,19 @@ static DEFINE_MUTEX(spec_ctrl_mutex);
    * Keep track of the SPEC_CTRL MSR value for the current task, which may differ
    * from x86_spec_ctrl_base due to STIBP/SSB in __speculation_ctrl_update().
    */
    -void write_spec_ctrl_current(u64 val)
    +void write_spec_ctrl_current(u64 val, bool force)
    {
    if (this_cpu_read(x86_spec_ctrl_current) == val)
    return;

    this_cpu_write(x86_spec_ctrl_current, val);
    - wrmsrl(MSR_IA32_SPEC_CTRL, val);
    +
    + /*
    + * When KERNEL_IBRS this MSR is written on return-to-user, unless
    + * forced the update can be delayed until that time.
    + */
    + if (force || !cpu_feature_enabled(X86_FEATURE_KERNEL_IBRS))
    + wrmsrl(MSR_IA32_SPEC_CTRL, val);
    }

    /*
    @@ -1290,7 +1296,7 @@ static void __init spectre_v2_select_mit
    if (spectre_v2_in_eibrs_mode(mode)) {
    /* Force it so VMEXIT will restore correctly */
    x86_spec_ctrl_base |= SPEC_CTRL_IBRS;
    - write_spec_ctrl_current(x86_spec_ctrl_base);
    + write_spec_ctrl_current(x86_spec_ctrl_base, true);
    }

    switch (mode) {
    @@ -1345,7 +1351,7 @@ static void __init spectre_v2_select_mit

    static void update_stibp_msr(void * __unused)
    {
    - write_spec_ctrl_current(x86_spec_ctrl_base);
    + write_spec_ctrl_current(x86_spec_ctrl_base, true);
    }

    /* Update x86_spec_ctrl_base in case SMT state changed. */
    @@ -1588,7 +1594,7 @@ static enum ssb_mitigation __init __ssb_
    x86_amd_ssb_disable();
    } else {
    x86_spec_ctrl_base |= SPEC_CTRL_SSBD;
    - write_spec_ctrl_current(x86_spec_ctrl_base);
    + write_spec_ctrl_current(x86_spec_ctrl_base, true);
    }
    }

    @@ -1839,7 +1845,7 @@ int arch_prctl_spec_ctrl_get(struct task
    void x86_spec_ctrl_setup_ap(void)
    {
    if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
    - write_spec_ctrl_current(x86_spec_ctrl_base);
    + write_spec_ctrl_current(x86_spec_ctrl_base, true);

    if (ssb_mode == SPEC_STORE_BYPASS_DISABLE)
    x86_amd_ssb_disable();
    --- a/arch/x86/kernel/process.c
    +++ b/arch/x86/kernel/process.c
    @@ -584,7 +584,7 @@ static __always_inline void __speculatio
    }

    if (updmsr)
    - write_spec_ctrl_current(msr);
    + write_spec_ctrl_current(msr, false);
    }

    static unsigned long speculation_ctrl_update_tif(struct task_struct *tsk)

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