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    Subject[PATCH 5.15 193/230] arm64: dts: imx8mp-phyboard-pollux-rdk: correct eqos pad settings
    Date
    From: Peng Fan <peng.fan@nxp.com>

    [ Upstream commit bae4de618efe1c41d34aa2e6cef8b08e46256667 ]

    BIT3 and BIT0 are reserved bits, should not touch.

    Fixes: 6f96852619d5 ("arm64: dts: freescale: Add support EQOS MAC on phyBOARD-Pollux-i.MX8MP")
    Signed-off-by: Peng Fan <peng.fan@nxp.com>
    Reviewed-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
    Signed-off-by: Shawn Guo <shawnguo@kernel.org>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    .../freescale/imx8mp-phyboard-pollux-rdk.dts | 28 +++++++++----------
    1 file changed, 14 insertions(+), 14 deletions(-)

    diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
    index e34076954897..cefd3d36f93f 100644
    --- a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
    +++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
    @@ -116,20 +116,20 @@
    &iomuxc {
    pinctrl_eqos: eqosgrp {
    fsl,pins = <
    - MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
    - MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
    - MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
    - MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
    - MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
    - MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
    - MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
    - MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
    - MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
    - MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
    - MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
    - MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
    - MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
    - MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
    + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
    + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
    + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
    + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
    + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
    + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
    + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
    + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
    + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
    + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
    + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
    + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
    + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
    + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
    MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x10
    >;
    };
    --
    2.35.1


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