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    Subject[PATCH 5.15 192/230] arm64: dts: imx8mp-phyboard-pollux-rdk: correct uart pad settings
    Date
    From: Peng Fan <peng.fan@nxp.com>

    [ Upstream commit e266c155bd88e95f9b86379d6b0add6ac6e5452e ]

    BIT3 and BIT0 are reserved bits, should not touch.

    Fixes: 846f752866bd ("arm64: dts: imx8mp-phyboard-pollux-rdk: Change debug UART")
    Signed-off-by: Peng Fan <peng.fan@nxp.com>
    Reviewed-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
    Signed-off-by: Shawn Guo <shawnguo@kernel.org>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts | 4 ++--
    1 file changed, 2 insertions(+), 2 deletions(-)

    diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
    index 984a6b9ded8d..e34076954897 100644
    --- a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
    +++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
    @@ -156,8 +156,8 @@

    pinctrl_uart1: uart1grp {
    fsl,pins = <
    - MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x49
    - MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x49
    + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x40
    + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x40
    >;
    };

    --
    2.35.1


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