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    Subject[PATCH 5.15 183/230] arm64: dts: qcom: sdm845: use dispcc AHB clock for mdss node
    Date
    From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

    [ Upstream commit 3ba500dee327e0261e728edec8a4f2f563d2760c ]

    It was noticed that on sdm845 after an MDSS suspend/resume cycle the
    driver can not read HW_REV registers properly (they will return 0
    instead). Chaning the "iface" clock from <&gcc GCC_DISP_AHB_CLK> to
    <&dispcc DISP_CC_MDSS_AHB_CLK> fixes the issue.

    Fixes: 08c2a076d18f ("arm64: dts: qcom: sdm845: Add dpu to sdm845 dts file")
    Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
    Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
    Link: https://lore.kernel.org/r/20220531124735.1165582-1-dmitry.baryshkov@linaro.org
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +-
    1 file changed, 1 insertion(+), 1 deletion(-)

    diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
    index d20eacfc1017..ea7a272d267a 100644
    --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
    +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
    @@ -4147,7 +4147,7 @@

    power-domains = <&dispcc MDSS_GDSC>;

    - clocks = <&gcc GCC_DISP_AHB_CLK>,
    + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
    <&dispcc DISP_CC_MDSS_MDP_CLK>;
    clock-names = "iface", "core";

    --
    2.35.1


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