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    Subject[PATCH 5.15 033/230] drm/i915: Replace the unconditional clflush with drm_clflush_virt_range()
    Date
    From: Ville Syrjälä <ville.syrjala@linux.intel.com>

    [ Upstream commit ef7ec41f17cbc0861891ccc0634d06a0c8dcbf09 ]

    Not all machines have clflush, so don't go assuming they do.
    Not really sure why the clflush is even here since hwsp
    is supposed to get snooped I thought.

    Although in my case we're talking about a i830 machine where
    render/blitter snooping is definitely busted. But it might
    work for the hswp perhaps. Haven't really reverse engineered
    that one fully.

    Cc: stable@vger.kernel.org
    Cc: Chris Wilson <chris@chris-wilson.co.uk>
    Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
    Fixes: b436a5f8b6c8 ("drm/i915/gt: Track all timelines created using the HWSP")
    Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
    Link: https://patchwork.freedesktop.org/patch/msgid/20211014090941.12159-2-ville.syrjala@linux.intel.com
    Reviewed-by: Dave Airlie <airlied@redhat.com>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/gpu/drm/i915/gt/intel_ring_submission.c | 2 +-
    1 file changed, 1 insertion(+), 1 deletion(-)

    diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
    index 6f2f6ba87397..02e18e70c78e 100644
    --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
    +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
    @@ -292,7 +292,7 @@ static void xcs_sanitize(struct intel_engine_cs *engine)
    sanitize_hwsp(engine);

    /* And scrub the dirty cachelines for the HWSP */
    - clflush_cache_range(engine->status_page.addr, PAGE_SIZE);
    + drm_clflush_virt_range(engine->status_page.addr, PAGE_SIZE);

    intel_engine_reset_pinned_contexts(engine);
    }
    --
    2.35.1


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