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    Subject[PATCH 5.18 067/112] arm64: dts: imx8mp-phyboard-pollux-rdk: correct i2c2 & mmc settings
    Date
    From: Peng Fan <peng.fan@nxp.com>

    [ Upstream commit 242d8ee9111171a6e68249aaff62643c513be6ec ]

    BIT3 and BIT0 are reserved bits, should not touch.

    Fixes: 88f7f6bcca37 ("arm64: dts: freescale: Add support for phyBOARD-Pollux-i.MX8MP")
    Signed-off-by: Peng Fan <peng.fan@nxp.com>
    Reviewed-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
    Signed-off-by: Shawn Guo <shawnguo@kernel.org>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    .../dts/freescale/imx8mp-phyboard-pollux-rdk.dts | 16 ++++++++--------
    1 file changed, 8 insertions(+), 8 deletions(-)

    diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
    index cefd3d36f93f..6aa720bafe28 100644
    --- a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
    +++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
    @@ -136,21 +136,21 @@

    pinctrl_i2c2: i2c2grp {
    fsl,pins = <
    - MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3
    - MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3
    + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
    + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
    >;
    };

    pinctrl_i2c2_gpio: i2c2gpiogrp {
    fsl,pins = <
    - MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1e3
    - MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1e3
    + MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1e2
    + MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1e2
    >;
    };

    pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
    fsl,pins = <
    - MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41
    + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
    >;
    };

    @@ -175,7 +175,7 @@
    MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
    MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
    MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
    - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
    + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
    >;
    };

    @@ -187,7 +187,7 @@
    MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
    MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
    MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
    - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
    + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
    >;
    };

    @@ -199,7 +199,7 @@
    MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
    MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
    MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
    - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
    + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
    >;
    };
    };
    --
    2.35.1


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