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    Subject[PATCH 5.18 054/112] arm64: dts: qcom: msm8994: Fix CPU6/7 reg values
    Date
    From: Konrad Dybcio <konrad.dybcio@somainline.org>

    [ Upstream commit 47bf59c4755930f616dd90c8c6a85f40a6d347ea ]

    CPU6 and CPU7 were mistakengly pointing to CPU5 reg. Fix it.

    Fixes: 02d8091bbca0 ("arm64: dts: qcom: msm8994: Add a proper CPU map")
    Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
    Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
    Link: https://lore.kernel.org/r/20220501184016.64138-1-konrad.dybcio@somainline.org
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    arch/arm64/boot/dts/qcom/msm8994.dtsi | 4 ++--
    1 file changed, 2 insertions(+), 2 deletions(-)

    diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi
    index b1e595cb4b90..6b76321288d0 100644
    --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi
    +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi
    @@ -93,7 +93,7 @@
    CPU6: cpu@102 {
    device_type = "cpu";
    compatible = "arm,cortex-a57";
    - reg = <0x0 0x101>;
    + reg = <0x0 0x102>;
    enable-method = "psci";
    next-level-cache = <&L2_1>;
    };
    @@ -101,7 +101,7 @@
    CPU7: cpu@103 {
    device_type = "cpu";
    compatible = "arm,cortex-a57";
    - reg = <0x0 0x101>;
    + reg = <0x0 0x103>;
    enable-method = "psci";
    next-level-cache = <&L2_1>;
    };
    --
    2.35.1


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