Messages in this thread Patch in this message | | | From | Krzysztof Kozlowski <> | Subject | [PATCH RFT] arm64: dts: qcom: sm6125: fix SDHCI CQE reg names | Date | Mon, 11 Jul 2022 10:26:48 +0200 |
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SM6125 comes with SDCC (SDHCI controller) v5, so the second range of registers is cqhci, not core.
Fixes: cff4bbaf2a2d ("arm64: dts: qcom: Add support for SM6125") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Not tested on hardware, but no practical impact is expected, because supports-cqe is not defined. --- arch/arm64/boot/dts/qcom/sm6125.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi index 77bff81af433..7664ef7e4da9 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -438,7 +438,7 @@ rpm_msg_ram: sram@45f0000 { sdhc_1: mmc@4744000 { compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5"; reg = <0x04744000 0x1000>, <0x04745000 0x1000>; - reg-names = "hc", "core"; + reg-names = "hc", "cqhci"; interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; -- 2.34.1
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