Messages in this thread | | | From | Guo Ren <> | Date | Tue, 12 Jul 2022 09:45:03 +0800 | Subject | Re: [v3 1/5] RISC-V: Fix counter restart during overflow for RV32 |
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Reviewed-by: Guo Ren <guoren@kernel.org>
On Tue, Jul 12, 2022 at 1:46 AM Atish Patra <atishp@rivosinc.com> wrote: > > Pass the upper half of the initial value of the counter correctly > for RV32. > > Fixes: 4905ec2fb7e6 ("RISC-V: Add sscofpmf extension support") > > Signed-off-by: Atish Patra <atishp@rivosinc.com> > --- > drivers/perf/riscv_pmu_sbi.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c > index dca3537a8dcc..0cb694b794ae 100644 > --- a/drivers/perf/riscv_pmu_sbi.c > +++ b/drivers/perf/riscv_pmu_sbi.c > @@ -525,8 +525,13 @@ static inline void pmu_sbi_start_overflow_mask(struct riscv_pmu *pmu, > hwc = &event->hw; > max_period = riscv_pmu_ctr_get_width_mask(event); > init_val = local64_read(&hwc->prev_count) & max_period; > +#if defined(CONFIG_32BIT) > + sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx, 1, > + flag, init_val, init_val >> 32, 0); > +#else > sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx, 1, > flag, init_val, 0, 0); > +#endif > } > ctr_ovf_mask = ctr_ovf_mask >> 1; > idx++; > -- > 2.25.1 >
-- Best Regards Guo Ren
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