Messages in this thread | | | From | Atish Patra <> | Date | Mon, 11 Jul 2022 13:39:12 -0700 | Subject | Re: [PATCH v4] arch/riscv: add Zihintpause support |
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On Mon, Jun 20, 2022 at 1:15 PM Dao Lu <daolu@rivosinc.com> wrote: > > Implement support for the ZiHintPause extension. > > The PAUSE instruction is a HINT that indicates the current hart’s rate > of instruction retirement should be temporarily reduced or paused. > > Reviewed-by: Heiko Stuebner <heiko@sntech.de> > Tested-by: Heiko Stuebner <heiko@sntech.de> > Signed-off-by: Dao Lu <daolu@rivosinc.com> > --- > > v1 -> v2: > Remove the usage of static branch, use PAUSE if toolchain supports it > v2 -> v3: > Added the static branch back, cpu_relax() behavior is kept the same for > systems that do not support ZiHintPause > v3 -> v4: > Adopted the newly added unified static keys for extensions > --- > arch/riscv/Makefile | 4 ++++ > arch/riscv/include/asm/hwcap.h | 5 +++++ > arch/riscv/include/asm/vdso/processor.h | 21 ++++++++++++++++++--- > arch/riscv/kernel/cpu.c | 1 + > arch/riscv/kernel/cpufeature.c | 1 + > 5 files changed, 29 insertions(+), 3 deletions(-) > > diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile > index 34cf8a598617..6ddacc6f44b9 100644 > --- a/arch/riscv/Makefile > +++ b/arch/riscv/Makefile > @@ -56,6 +56,10 @@ riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c > toolchain-need-zicsr-zifencei := $(call cc-option-yn, -march=$(riscv-march-y)_zicsr_zifencei) > riscv-march-$(toolchain-need-zicsr-zifencei) := $(riscv-march-y)_zicsr_zifencei > > +# Check if the toolchain supports Zihintpause extension > +toolchain-supports-zihintpause := $(call cc-option-yn, -march=$(riscv-march-y)_zihintpause) > +riscv-march-$(toolchain-supports-zihintpause) := $(riscv-march-y)_zihintpause > + > KBUILD_CFLAGS += -march=$(subst fd,,$(riscv-march-y)) > KBUILD_AFLAGS += -march=$(riscv-march-y) > > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h > index e48eebdd2631..dc47019a0b38 100644 > --- a/arch/riscv/include/asm/hwcap.h > +++ b/arch/riscv/include/asm/hwcap.h > @@ -8,6 +8,7 @@ > #ifndef _ASM_RISCV_HWCAP_H > #define _ASM_RISCV_HWCAP_H > > +#include <asm/errno.h> > #include <linux/bits.h> > #include <uapi/asm/hwcap.h> > > @@ -54,6 +55,7 @@ extern unsigned long elf_hwcap; > enum riscv_isa_ext_id { > RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE, > RISCV_ISA_EXT_SVPBMT, > + RISCV_ISA_EXT_ZIHINTPAUSE, > RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX, > }; > > @@ -64,6 +66,7 @@ enum riscv_isa_ext_id { > */ > enum riscv_isa_ext_key { > RISCV_ISA_EXT_KEY_FPU, /* For 'F' and 'D' */ > + RISCV_ISA_EXT_KEY_ZIHINTPAUSE, > RISCV_ISA_EXT_KEY_MAX, > }; > > @@ -83,6 +86,8 @@ static __always_inline int riscv_isa_ext2key(int num) > return RISCV_ISA_EXT_KEY_FPU; > case RISCV_ISA_EXT_d: > return RISCV_ISA_EXT_KEY_FPU; > + case RISCV_ISA_EXT_ZIHINTPAUSE: > + return RISCV_ISA_EXT_KEY_ZIHINTPAUSE; > default: > return -EINVAL; > } > diff --git a/arch/riscv/include/asm/vdso/processor.h b/arch/riscv/include/asm/vdso/processor.h > index 134388cbaaa1..1e4f8b4aef79 100644 > --- a/arch/riscv/include/asm/vdso/processor.h > +++ b/arch/riscv/include/asm/vdso/processor.h > @@ -4,15 +4,30 @@ > > #ifndef __ASSEMBLY__ > > +#include <linux/jump_label.h> > #include <asm/barrier.h> > +#include <asm/hwcap.h> > > static inline void cpu_relax(void) > { > + if (!static_branch_likely(&riscv_isa_ext_keys[RISCV_ISA_EXT_KEY_ZIHINTPAUSE])) { > #ifdef __riscv_muldiv > - int dummy; > - /* In lieu of a halt instruction, induce a long-latency stall. */ > - __asm__ __volatile__ ("div %0, %0, zero" : "=r" (dummy)); > + int dummy; > + /* In lieu of a halt instruction, induce a long-latency stall. */ > + __asm__ __volatile__ ("div %0, %0, zero" : "=r" (dummy)); > #endif > + } else { > + /* > + * Reduce instruction retirement. > + * This assumes the PC changes. > + */ > +#ifdef __riscv_zihintpause > + __asm__ __volatile__ ("pause"); > +#else > + /* Encoding of the pause instruction */ > + __asm__ __volatile__ (".4byte 0x100000F"); > +#endif > + } > barrier(); > } > > diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c > index fba9e9f46a8c..a123e92b14dd 100644 > --- a/arch/riscv/kernel/cpu.c > +++ b/arch/riscv/kernel/cpu.c > @@ -89,6 +89,7 @@ int riscv_of_parent_hartid(struct device_node *node) > static struct riscv_isa_ext_data isa_ext_arr[] = { > __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), > __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), > + __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), > __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX), > }; > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > index 1b3ec44e25f5..708df2c0bc34 100644 > --- a/arch/riscv/kernel/cpufeature.c > +++ b/arch/riscv/kernel/cpufeature.c > @@ -198,6 +198,7 @@ void __init riscv_fill_hwcap(void) > } else { > SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF); > SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT); > + SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE); > } > #undef SET_ISA_EXT_MAP > } > -- > 2.25.1 >
LGTM.
Reviewed-by: Atish Patra <atishp@rivosinc.com> -- Regards, Atish
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