Messages in this thread | | | Date | Mon, 11 Jul 2022 17:32:50 +0000 | From | Yazen Ghannam <> | Subject | Re: [PATCH 2/3] x86/MCE/APEI: Handle variable register array size |
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On Sun, Jul 03, 2022 at 02:30:24PM +0200, Borislav Petkov wrote: > On Mon, Apr 18, 2022 at 05:44:39PM +0000, Yazen Ghannam wrote: > > Recent AMD systems may provide an x86 Common Platform Error Record > > (CPER) for errors reported in the ACPI Boot Error Record Table (BERT). > > The x86 CPER may contain one or more Processor Context Information > > Structures. The context structures may represent an x86 MSR range where > > a starting address is given, and the data represents a contiguous set of > > MSRs starting from, and including, the starting address. > > You're killing me with these "may" formulations. Just say it once and > then drop it. I mean, we know some future hw "may" support something > new - you can just as well drop the "may" thing because if it only may > and it turns out it might not, you don't even have to do the work and > enabling it and sending the patch. > > So no need to do that - the patch commit message should talk purely > about functionality and not sound like some vendor doc - there are > enough of those. >
Understood.
Thanks, Yazen
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