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SubjectRE: [PATCH v7 0/5] Add Aspeed crypto driver for hardware acceleration
Date
> -----Original Message-----
> From: Neal Liu <neal_liu@aspeedtech.com>
> Sent: Tuesday, July 5, 2022 10:10 AM
> To: Corentin Labbe <clabbe.montjoie@gmail.com>; Christophe JAILLET
> <christophe.jaillet@wanadoo.fr>; Randy Dunlap <rdunlap@infradead.org>;
> Herbert Xu <herbert@gondor.apana.org.au>; David S . Miller
> <davem@davemloft.net>; Rob Herring <robh+dt@kernel.org>; Krzysztof
> Kozlowski <krzysztof.kozlowski+dt@linaro.org>; Joel Stanley <joel@jms.id.au>;
> Andrew Jeffery <andrew@aj.id.au>; Dhananjay Phadke
> <dhphadke@microsoft.com>; Johnny Huang
> <johnny_huang@aspeedtech.com>
> Cc: linux-aspeed@lists.ozlabs.org; linux-crypto@vger.kernel.org;
> devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> linux-kernel@vger.kernel.org; BMC-SW <BMC-SW@aspeedtech.com>
> Subject: [PATCH v7 0/5] Add Aspeed crypto driver for hardware acceleration

Gentle ping on these patch series, thanks.

> Aspeed Hash and Crypto Engine (HACE) is designed to accelerate the
> throughput of hash data digest, encryption and decryption.
>
> These patches aim to add Aspeed hash & crypto driver support.
> The hash & crypto driver also pass the run-time self tests that take place at
> algorithm registration.
>
> The patch series are tested on both AST2500 & AST2600 evaluation boards.
>
> Tested-by below configs:
> - CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set
> - CONFIG_CRYPTO_MANAGER_EXTRA_TESTS=y
> - CONFIG_DMA_API_DEBUG=y
> - CONFIG_DMA_API_DEBUG_SG=y
> - CONFIG_CPU_BIG_ENDIAN=y
>
> Change since v6:
> - Refine debug print.
> - Change aspeed_sg_list struct memeber's type to __le32.
>
> Change since v5:
> - Re-define HACE clock define to fix breaking ABI.
>
> Change since v4:
> - Add AST2500 clock definition & dts node.
> - Add software fallback for handling corner cases.
> - Fix copy wrong key length.
>
> Change since v3:
> - Use dmam_alloc_coherent() instead to manage dma_alloc_coherent().
> - Add more error handler of dma_prepare() & crypto_engine_start().
>
> Change since v2:
> - Fix endianness issue. Tested on both little endian & big endian
> system.
> - Use common crypto hardware engine for enqueue & dequeue requests.
> - Use pre-defined IVs for SHA-family.
> - Revise error handler flow.
> - Fix sorts of coding style problems.
>
> Change since v1:
> - Add more error handlers, including DMA memory allocate/free, DMA
> map/unmap, clock enable/disable, etc.
> - Fix check dma_map error for config DMA_API_DEBUG.
> - Fix dt-binding doc & dts node naming.
>
>
> Neal Liu (5):
> crypto: aspeed: Add HACE hash driver
> dt-bindings: clock: Add AST2500/AST2600 HACE reset definition
> ARM: dts: aspeed: Add HACE device controller node
> dt-bindings: crypto: add documentation for aspeed hace
> crypto: aspeed: add HACE crypto driver
>
> .../bindings/crypto/aspeed,ast2500-hace.yaml | 53 +
> MAINTAINERS | 7 +
> arch/arm/boot/dts/aspeed-g5.dtsi | 8 +
> arch/arm/boot/dts/aspeed-g6.dtsi | 8 +
> drivers/crypto/Kconfig | 1 +
> drivers/crypto/Makefile | 1 +
> drivers/crypto/aspeed/Kconfig | 40 +
> drivers/crypto/aspeed/Makefile | 9 +
> drivers/crypto/aspeed/aspeed-hace-crypto.c | 1121 +++++++++++++
> drivers/crypto/aspeed/aspeed-hace-hash.c | 1428
> +++++++++++++++++
> drivers/crypto/aspeed/aspeed-hace.c | 302 ++++
> drivers/crypto/aspeed/aspeed-hace.h | 293 ++++
> include/dt-bindings/clock/aspeed-clock.h | 1 +
> include/dt-bindings/clock/ast2600-clock.h | 1 +
> 14 files changed, 3273 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/crypto/aspeed,ast2500-hace.yaml
> create mode 100644 drivers/crypto/aspeed/Kconfig create mode 100644
> drivers/crypto/aspeed/Makefile create mode 100644
> drivers/crypto/aspeed/aspeed-hace-crypto.c
> create mode 100644 drivers/crypto/aspeed/aspeed-hace-hash.c
> create mode 100644 drivers/crypto/aspeed/aspeed-hace.c
> create mode 100644 drivers/crypto/aspeed/aspeed-hace.h
>
> --
> 2.25.1

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