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    SubjectRe: [PATCH v2 6/6] ASoC: dt-bindings: fsl-sai: Add two PLL clock source
    On Fri, 01 Jul 2022 17:32:41 +0800, Shengjiu Wang wrote:
    > Add two PLL clock source, they are the parent clocks of root clock
    > one is for 8kHz series rates, another one is for 11kHz series rates.
    > They are optional clocks, if there are such clocks, then driver
    > can switch between them for supporting more accurate rates.
    >
    > Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
    > ---
    > Documentation/devicetree/bindings/sound/fsl-sai.txt | 3 +++
    > 1 file changed, 3 insertions(+)
    >

    Acked-by: Rob Herring <robh@kernel.org>

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