Messages in this thread | | | From | Samuel Holland <> | Subject | [PATCH v3 0/2] irqchip: RISC-V PLIC cleanup and optimization | Date | Fri, 1 Jul 2022 15:24:38 -0500 |
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This series removes the spinlocks and cpumask operations from the PLIC driver's hot path. As far as I know, using the priority to mask interrupts is an intended usage and will work on all existing implementations. See [1] for more discussion.
This series depends on my other series[2] making the IRQ affinity mask behavior more consistent between uniprocessor and SMP configurations. (The Allwinner D1 is a uniprocessor SoC containing a PLIC.)
A further optimization is to take advantage of the fact that multiple IRQs can be claimed at once. This allows removing the mask operations for oneshot IRQs -- i.e. the combination of IRQCHIP_ONESHOT_SAFE and IRQCHIP_EOI_THREADED, which is not currently supported. I will send this as a separate series, since it makes more invasive changes to the generic IRQ code.
[1]: https://lore.kernel.org/lkml/2b063917-17c8-0add-fadf-5aa42532fbbf@sholland.org/ [2]: https://lore.kernel.org/lkml/20220701200056.46555-1-samuel@sholland.org/
Changes in v3: - Rebased on top of irqchip-next - Split affinity series and PLIC series
Samuel Holland (2): irqchip/sifive-plic: Make better use of the effective affinity mask irqchip/sifive-plic: Separate the enable and mask operations
drivers/irqchip/Kconfig | 1 + drivers/irqchip/irq-sifive-plic.c | 64 ++++++++++++++++--------------- 2 files changed, 35 insertions(+), 30 deletions(-)
-- 2.35.1
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