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SubjectRe: [PATCH v10 18/21] drm/mediatek: Add mt8195 Embedded DisplayPort driver
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On Wed, 2022-06-08 at 16:30 +0800, CK Hu wrote:
> Hi, Rex:
>
> On Mon, 2022-05-23 at 12:47 +0200, Guillaume Ranquet wrote:
> > From: Markus Schneider-Pargmann <msp@baylibre.com>
> >
> > This patch adds a DisplayPort driver for the Mediatek mt8195 SoC.
> >
> > It supports the mt8195, the embedded DisplayPort units. It offers
> > DisplayPort 1.4 with up to 4 lanes.
> >
> > The driver creates a child device for the phy. The child device
> > will
> > never exist without the parent being active. As they are sharing a
> > register range, the parent passes a regmap pointer to the child so
> > that
> > both can work with the same register range. The phy driver sets
> > device
> > data that is read by the parent to get the phy device that can be
> > used
> > to control the phy properties.
> >
> > This driver is based on an initial version by
> > Jason-JH.Lin <jason-jh.lin@mediatek.com>.
> >
> > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
> > Signed-off-by: Guillaume Ranquet <granquet@baylibre.com>
> > ---
>
> [snip]
>
> > +
> > +static bool mtk_dp_parse_capabilities(struct mtk_dp *mtk_dp)
> > +{
> > + u8 buf[DP_RECEIVER_CAP_SIZE] = {};
> > + u8 val;
> > + struct mtk_dp_train_info *train_info = &mtk_dp->train_info;
> > +
> > + if (!mtk_dp_plug_state(mtk_dp))
> > + return false;
> > +
> > + drm_dp_dpcd_writeb(&mtk_dp->aux, DP_SET_POWER,
> > DP_SET_POWER_D0);
> > + /* Wait for power on */
> > + usleep_range(2000, 5000);
> > +
> > + drm_dp_read_dpcd_caps(&mtk_dp->aux, buf);
> > +
> > + memcpy(mtk_dp->rx_cap, buf, min(sizeof(mtk_dp->rx_cap),
> > sizeof(buf)));
>
> sizeof(mtk_dp->rx_cap) is identical to sizeof(buf), so
>
> drm_dp_read_dpcd_caps(&mtk_dp->aux, mtk_dp->rx_cap);
>
>

Hello CK,

I will drop buf[].

> > + mtk_dp->rx_cap[DP_TRAINING_AUX_RD_INTERVAL] &=
> > DP_TRAINING_AUX_RD_MASK;
> > +
> > + train_info->link_rate =
> > + min_t(int, mtk_dp->max_linkrate, buf[mtk_dp-
> > > max_linkrate]);
> >
> > + train_info->lane_count =
> > + min_t(int, mtk_dp->max_lanes,
> > drm_dp_max_lane_count(buf));
> > +
> > + train_info->tps3 = drm_dp_tps3_supported(buf);
> > + train_info->tps4 = drm_dp_tps4_supported(buf);
> > +
> > + train_info->sink_ssc =
> > + !!(buf[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5);
> > +
> > + train_info->sink_ssc = false;
>
> What does these two statement do?
>

ssc = Spread spectrum clock.
it's for both edp and dp.

BRs,
Bo-Chen

> Regards,
> CK
>
> > +
> > + drm_dp_dpcd_readb(&mtk_dp->aux, DP_MSTM_CAP, &val);
> > + if (val & DP_MST_CAP) {
> > + /* Clear DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 */
> > + drm_dp_dpcd_readb(&mtk_dp->aux,
> > + DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0,
> > &val);
> > + if (val)
> > + drm_dp_dpcd_writeb(&mtk_dp->aux,
> > + DP_DEVICE_SERVICE_IRQ_VECTOR
> > _ESI0,
> > + val);
> > + }
> > +
> > + return true;
> > +}
> > +
>
>

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