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SubjectRe: [PATCH v4 1/1] MAINTAINERS: add polarfire rng, pci and clock drivers
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Quoting Palmer Dabbelt (2022-06-01 18:55:40)
> On Mon, 23 May 2022 13:00:01 PDT (-0700), Conor.Dooley@microchip.com wrote:
> > On 23/05/2022 20:52, Palmer Dabbelt wrote:
> >> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >>
> >> On Mon, 23 May 2022 04:42:53 PDT (-0700), Conor.Dooley@microchip.com wrote:
> >>> On 05/05/2022 11:55, Conor Dooley wrote:
> >>>> Hardware random, PCI and clock drivers for the PolarFire SoC have been
> >>>> upstreamed but are not covered by the MAINTAINERS entry, so add them.
> >>>> Daire is the author of the clock & PCI drivers, so add him as a
> >>>> maintainer in place of Lewis.
> >>>>
> >>>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> >>>
> >>> Hey Palmer,
> >>> I know youre busy etc but just a reminder :)
> >>
> >> Sorry, I didn't realize this was aimed at the RISC-V tree.�� I'm fine
> >> taking it, but it seems like these should have gone in along with the
> >> drivers.
> >
> > Yeah, sorry. In hindsight it should've but that ship has sailed. I sent
> > the rng bundled this way b/c I didn't want to end up a conflict.
> > Obv. there's not a rush so I can always split it back out if needs be.
>
> I'm adding a bunch of subsystem maintainers just to check again. I
> don't have any problem with it, just not really a RISC-V thing and don't
> wan to make a mess. I've stashed it over at palmer/pcsoc-maintainers
> for now.
>

Acked-by: Stephen Boyd <sboyd@kernel.org>

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