Messages in this thread | | | From | Tomer Maimon <> | Date | Fri, 10 Jun 2022 01:42:42 +0300 | Subject | Re: [PATCH v2 07/20] clk: npcm8xx: add clock controller |
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Hi Stephen,
Thanks for your comment, it will be addressed next patch set
On Fri, 10 Jun 2022 at 01:14, Stephen Boyd <sboyd@kernel.org> wrote: > > Quoting Tomer Maimon (2022-06-08 02:56:10) > > diff --git a/drivers/clk/clk-npcm8xx.c b/drivers/clk/clk-npcm8xx.c > > new file mode 100644 > > index 000000000000..40340c3611b5 > > --- /dev/null > > +++ b/drivers/clk/clk-npcm8xx.c > > @@ -0,0 +1,756 @@ > [...] > > + > > +#define PLLCON_LOKI BIT(31) > > +#define PLLCON_LOKS BIT(30) > > +#define PLLCON_FBDV GENMASK(27, 16) > > +#define PLLCON_OTDV2 GENMASK(15, 13) > > +#define PLLCON_PWDEN BIT(12) > > +#define PLLCON_OTDV1 GENMASK(10, 8) > > +#define PLLCON_INDV GENMASK(5, 0) > > + > > +static unsigned long npcm8xx_clk_pll_recalc_rate(struct clk_hw *hw, > > + unsigned long parent_rate) > > +{ > > + struct npcm8xx_clk_pll *pll = to_npcm8xx_clk_pll(hw); > > + unsigned long fbdv, indv, otdv1, otdv2; > > + unsigned int val; > > + u64 ret; > > + > > + if (parent_rate == 0) { > > + pr_debug("%s: parent rate is zero", __func__); > > Missing newline. > > > + return 0; > > + } > > + > > + val = readl_relaxed(pll->pllcon); > > + > > + indv = FIELD_GET(PLLCON_INDV, val);
Best regards,
Tomer
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