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    Subject[PATCH v8 05/14] dt-bindings: display: bridge: Add i.MX8qm/qxp display pixel link binding
    Date
    This patch adds bindings for i.MX8qm/qxp display pixel link.

    Reviewed-by: Rob Herring <robh@kernel.org>
    Signed-off-by: Liu Ying <victor.liu@nxp.com>
    ---
    v7->v8:
    * No change.

    v6->v7:
    * No change.

    v5->v6:
    * No change.

    v4->v5:
    * No change.

    v3->v4:
    * No change.

    v2->v3:
    * Add Rob's R-b tag.

    v1->v2:
    * Use graph schema. (Laurent)
    * Require all four pixel link output ports. (Laurent)
    * Mention pixel link is accessed via SCU firmware. (Rob)

    .../bridge/fsl,imx8qxp-pixel-link.yaml | 106 ++++++++++++++++++
    1 file changed, 106 insertions(+)
    create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml

    diff --git a/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml
    new file mode 100644
    index 000000000000..3af67ccf8db1
    --- /dev/null
    +++ b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml
    @@ -0,0 +1,106 @@
    +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
    +%YAML 1.2
    +---
    +$id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pixel-link.yaml#
    +$schema: http://devicetree.org/meta-schemas/core.yaml#
    +
    +title: Freescale i.MX8qm/qxp Display Pixel Link
    +
    +maintainers:
    + - Liu Ying <victor.liu@nxp.com>
    +
    +description: |
    + The Freescale i.MX8qm/qxp Display Pixel Link(DPL) forms a standard
    + asynchronous linkage between pixel sources(display controller or
    + camera module) and pixel consumers(imaging or displays).
    + It consists of two distinct functions, a pixel transfer function and a
    + control interface. Multiple pixel channels can exist per one control channel.
    + This binding documentation is only for pixel links whose pixel sources are
    + display controllers.
    +
    + The i.MX8qm/qxp Display Pixel Link is accessed via System Controller Unit(SCU)
    + firmware.
    +
    +properties:
    + compatible:
    + enum:
    + - fsl,imx8qm-dc-pixel-link
    + - fsl,imx8qxp-dc-pixel-link
    +
    + ports:
    + $ref: /schemas/graph.yaml#/properties/ports
    +
    + properties:
    + port@0:
    + $ref: /schemas/graph.yaml#/properties/port
    + description: The pixel link input port node from upstream video source.
    +
    + patternProperties:
    + "^port@[1-4]$":
    + $ref: /schemas/graph.yaml#/properties/port
    + description: The pixel link output port node to downstream bridge.
    +
    + required:
    + - port@0
    + - port@1
    + - port@2
    + - port@3
    + - port@4
    +
    +required:
    + - compatible
    + - ports
    +
    +additionalProperties: false
    +
    +examples:
    + - |
    + dc0-pixel-link0 {
    + compatible = "fsl,imx8qxp-dc-pixel-link";
    +
    + ports {
    + #address-cells = <1>;
    + #size-cells = <0>;
    +
    + /* from dc0 pixel combiner channel0 */
    + port@0 {
    + reg = <0>;
    +
    + dc0_pixel_link0_dc0_pixel_combiner_ch0: endpoint {
    + remote-endpoint = <&dc0_pixel_combiner_ch0_dc0_pixel_link0>;
    + };
    + };
    +
    + /* to PXL2DPIs in MIPI/LVDS combo subsystems */
    + port@1 {
    + #address-cells = <1>;
    + #size-cells = <0>;
    + reg = <1>;
    +
    + dc0_pixel_link0_mipi_lvds_0_pxl2dpi: endpoint@0 {
    + reg = <0>;
    + remote-endpoint = <&mipi_lvds_0_pxl2dpi_dc0_pixel_link0>;
    + };
    +
    + dc0_pixel_link0_mipi_lvds_1_pxl2dpi: endpoint@1 {
    + reg = <1>;
    + remote-endpoint = <&mipi_lvds_1_pxl2dpi_dc0_pixel_link0>;
    + };
    + };
    +
    + /* unused */
    + port@2 {
    + reg = <2>;
    + };
    +
    + /* unused */
    + port@3 {
    + reg = <3>;
    + };
    +
    + /* to imaging subsystem */
    + port@4 {
    + reg = <4>;
    + };
    + };
    + };
    --
    2.25.1
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