Messages in this thread | | | From | Andy Shevchenko <> | Date | Wed, 8 Jun 2022 12:50:44 +0200 | Subject | Re: [PATCH v6 00/12] platform/x86: introduce p2sb_bar() helper |
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On Wed, Jun 8, 2022 at 9:42 AM Lee Jones <lee.jones@linaro.org> wrote: > > On Mon, 06 Jun 2022, Andy Shevchenko wrote: > > > There are a few users that would like to utilize P2SB mechanism of hiding > > and unhiding a device from the PCI configuration space. > > > > Here is the series to consolidate p2sb handling code for existing users > > and to provide a generic way for new comer(s). > > > > It also includes a patch to enable GPIO controllers on Apollo Lake > > when it's used with ABL bootloader w/o ACPI support. > > > > The patch that brings the helper ("platform/x86/intel: Add Primary to > > Sideband (P2SB) bridge support") has a commit message that sheds a light > > on what the P2SB is and why this is needed. > > > > I have tested this on Apollo Lake platform (I'm able to see SPI NOR and > > since we have an ACPI device for GPIO I do not see any attempts to recreate > > one). > > > > The series is ready to be merged via MFD tree, but see below. > > > > The series also includes updates for Simatic IPC drivers that partially > > tagged by respective maintainers (the main question is if Pavel is okay > > with the last three patches, since I believe Hans is okay with removing > > some code under PDx86). Hence the first 8 patches can be merged right > > away and the rest when Pavel does his review. > > Can we just wait for Pavel's review, then merge them all at once?
Sure, it would be the best course of action.
-- With Best Regards, Andy Shevchenko
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