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SubjectRe: [PATCH v3 3/4] RISC-V: Added generic pmu-events mapfile
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On 07/06/2022 14:16, Nikita Shubin wrote:
> From: João Mário Domingos <joao.mario@tecnico.ulisboa.pt>
>
> The pmu-events now supports custom events for RISC-V, plus the cycle,
> time and instret events were defined.
>
> Signed-off-by: João Mário Domingos <joao.mario@tecnico.ulisboa.pt>
> Tested-by: Nikita Shubin <n.shubin@yadro.com>
> ---
> tools/perf/pmu-events/arch/riscv/mapfile.csv | 14 +++++++++++++
> .../pmu-events/arch/riscv/riscv-generic.json | 20 +++++++++++++++++++
> 2 files changed, 34 insertions(+)
> create mode 100644 tools/perf/pmu-events/arch/riscv/mapfile.csv
> create mode 100644 tools/perf/pmu-events/arch/riscv/riscv-generic.json
>
> diff --git a/tools/perf/pmu-events/arch/riscv/mapfile.csv b/tools/perf/pmu-events/arch/riscv/mapfile.csv
> new file mode 100644
> index 000000000000..4f2aa199d9cb
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/riscv/mapfile.csv
> @@ -0,0 +1,14 @@
> +# Format:
> +# MIDR,Version,JSON/file/pathname,Type
> +#
> +# where
> +# MIDR Processor version

ARM, no?

> +# Variant[23:20] and Revision [3:0] should be zero.
> +# Version could be used to track version of JSON file
> +# but currently unused.
> +# JSON/file/pathname is the path to JSON file, relative
> +# to tools/perf/pmu-events/arch/riscv/.
> +# Type is core, uncore etc
> +#
> +#
> +#Family-model,Version,Filename,EventType
> diff --git a/tools/perf/pmu-events/arch/riscv/riscv-generic.json b/tools/perf/pmu-events/arch/riscv/riscv-generic.json
> new file mode 100644
> index 000000000000..013e50efad99
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/riscv/riscv-generic.json

where or how are these referenced?

> @@ -0,0 +1,20 @@
> +[
> + {
> + "PublicDescription": "CPU Cycles",
> + "EventCode": "0x00",
> + "EventName": "riscv_cycles",
> + "BriefDescription": "CPU cycles RISC-V generic counter"
> + },
> + {
> + "PublicDescription": "CPU Time",
> + "EventCode": "0x01",
> + "EventName": "riscv_time",
> + "BriefDescription": "CPU time RISC-V generic counter"
> + },
> + {
> + "PublicDescription": "CPU Instructions",
> + "EventCode": "0x02",
> + "EventName": "riscv_instret",
> + "BriefDescription": "CPU retired instructions RISC-V generic counter"
> + }
> +]
> \ No newline at end of file

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