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Subject[PATCH v4 0/2] Add support for Xilinx Versal CPM5 Root Port
Xilinx Versal Premium series has CPM5 block which supports Root Port functioning at Gen5 speed.

Xilinx Versal CPM5 has few changes with existing CPM block.
- CPM5 has dedicated register space for control and status registers.
- CPM5 legacy interrupt handling needs additonal register bit
to enable and handle legacy interrupts.

Changes in v4:
- Removed versioning in compatible string
- reg property definitions are added

Bharat Kumar Gogada (2):
dt-bindings: PCI: xilinx-cpm: Add Versal CPM5 Root Port
PCI: xilinx-cpm: Add support for Versal CPM5 Root Port

.../bindings/pci/xilinx-versal-cpm.yaml | 48 +++++++++++++++++--
drivers/pci/controller/pcie-xilinx-cpm.c | 33 ++++++++++++-
2 files changed, 76 insertions(+), 5 deletions(-)


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