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SubjectRe: [PATCH v10 18/21] drm/mediatek: Add mt8195 Embedded DisplayPort driver
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On Tue, 2022-06-07 at 16:12 +0800, CK Hu wrote:
> Hi, Rex:
>
> On Mon, 2022-05-23 at 12:47 +0200, Guillaume Ranquet wrote:
> > From: Markus Schneider-Pargmann <msp@baylibre.com>
> >
> > This patch adds a DisplayPort driver for the Mediatek mt8195 SoC.
> >
> > It supports the mt8195, the embedded DisplayPort units. It offers
> > DisplayPort 1.4 with up to 4 lanes.
> >
> > The driver creates a child device for the phy. The child device
> > will
> > never exist without the parent being active. As they are sharing a
> > register range, the parent passes a regmap pointer to the child so
> > that
> > both can work with the same register range. The phy driver sets
> > device
> > data that is read by the parent to get the phy device that can be
> > used
> > to control the phy properties.
> >
> > This driver is based on an initial version by
> > Jason-JH.Lin <jason-jh.lin@mediatek.com>.
> >
> > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
> > Signed-off-by: Guillaume Ranquet <granquet@baylibre.com>
> > ---
>
> [snip]
>
> > +
> > +static int mtk_dp_train_start(struct mtk_dp *mtk_dp)
> > +{
> > + int ret = 0;
> > + u8 lane_count;
> > + u8 link_rate;
> > + u8 train_limit;
> > + u8 max_link_rate;
> > + u8 plug_wait;
> > +
> > + for (plug_wait = 7; !mtk_dp_plug_state(mtk_dp) && plug_wait >
> > 0;
> > + --plug_wait)
> > + /* Avoid short pulses on the HPD isr */
> > + usleep_range(1000, 5000);
> > + if (plug_wait == 0) {
> > + mtk_dp->train_state = MTK_DP_TRAIN_STATE_DPIDLE;
>
> After return, mtk_dp->train_state would be set to
> MTK_DP_TRAIN_STATE_DPIDLE, so drop this.
>

ok, I will do this.

> > + return -ENODEV;
> > + }
> > +
> > + link_rate = mtk_dp->rx_cap[1];
> > + lane_count = mtk_dp->rx_cap[2] & 0x1F;
> > +
> > + mtk_dp->train_info.link_rate = min(mtk_dp->max_linkrate,
> > link_rate);
> > + mtk_dp->train_info.lane_count = min(mtk_dp->max_lanes,
> > lane_count);
> > + link_rate = mtk_dp->train_info.link_rate;
> > + lane_count = mtk_dp->train_info.lane_count;
> > +
> > + switch (link_rate) {
> > + case MTK_DP_LINKRATE_RBR:
> > + case MTK_DP_LINKRATE_HBR:
> > + case MTK_DP_LINKRATE_HBR2:
> > + case MTK_DP_LINKRATE_HBR25:
> > + case MTK_DP_LINKRATE_HBR3:
> > + break;
> > + default:
> > + mtk_dp->train_info.link_rate = MTK_DP_LINKRATE_HBR3;
> > + break;
> > + };
> > +
> > + max_link_rate = link_rate;
> > + for (train_limit = 6; train_limit > 0; train_limit--) {
> > + mtk_dp->train_info.cr_done = false;
> > + mtk_dp->train_info.eq_done = false;
> > +
> > + mtk_dp_train_change_mode(mtk_dp);
> > + ret = mtk_dp_train_flow(mtk_dp, link_rate, lane_count);
> > + if (ret)
> > + return ret;
> > +
> > + if (!mtk_dp->train_info.cr_done) {
> > + switch (link_rate) {
> > + case MTK_DP_LINKRATE_RBR:
> > + lane_count = lane_count / 2;
> > + link_rate = max_link_rate;
> > + if (lane_count == 0) {
> > + mtk_dp->train_state =
> > + MTK_DP_TRAIN_STATE_DPID
> > LE;
>
> After return, mtk_dp->train_state would be set to
> MTK_DP_TRAIN_STATE_DPIDLE, so drop this.
>
> Regards,
> CK
>

ok.

> > + return -EIO;
> > + }
> > + break;
> > + case MTK_DP_LINKRATE_HBR:
> > + link_rate = MTK_DP_LINKRATE_RBR;
> > + break;
> > + case MTK_DP_LINKRATE_HBR2:
> > + link_rate = MTK_DP_LINKRATE_HBR;
> > + break;
> > + case MTK_DP_LINKRATE_HBR3:
> > + link_rate = MTK_DP_LINKRATE_HBR2;
> > + break;
> > + default:
> > + return -EINVAL;
> > + };
> > + } else if (!mtk_dp->train_info.eq_done) {
> > + if (lane_count == 0)
> > + return -EIO;
> > +
> > + lane_count /= 2;
> > + } else {
> > + break;
> > + }
> > + }
> > +
> > + if (train_limit == 0)
> > + return -ETIMEDOUT;
> > +
> > + return 0;
> > +}
> > +
>
>

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