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    Subject[tip: x86/mm] Documentation/protection-keys: Clean up documentation for User Space pkeys
    The following commit has been merged into the x86/mm branch of tip:

    Commit-ID: f8c1d4ca55177326adad1fdc6bf602423a507542
    Gitweb: https://git.kernel.org/tip/f8c1d4ca55177326adad1fdc6bf602423a507542
    Author: Ira Weiny <ira.weiny@intel.com>
    AuthorDate: Tue, 19 Apr 2022 10:06:06 -07:00
    Committer: Dave Hansen <dave.hansen@linux.intel.com>
    CommitterDate: Tue, 07 Jun 2022 16:06:22 -07:00

    Documentation/protection-keys: Clean up documentation for User Space pkeys

    The documentation for user space pkeys was a bit dated including things
    such as Amazon and distribution testing information which is irrelevant
    now.

    Update the documentation. This also streamlines adding the Supervisor
    pkey documentation later on.

    Signed-off-by: Ira Weiny <ira.weiny@intel.com>
    Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
    Link: https://lkml.kernel.org/r/20220419170649.1022246-2-ira.weiny@intel.com
    ---
    Documentation/core-api/protection-keys.rst | 44 ++++++++++-----------
    1 file changed, 21 insertions(+), 23 deletions(-)

    diff --git a/Documentation/core-api/protection-keys.rst b/Documentation/core-api/protection-keys.rst
    index ec575e7..bf28ac0 100644
    --- a/Documentation/core-api/protection-keys.rst
    +++ b/Documentation/core-api/protection-keys.rst
    @@ -4,31 +4,29 @@
    Memory Protection Keys
    ======================

    -Memory Protection Keys for Userspace (PKU aka PKEYs) is a feature
    -which is found on Intel's Skylake (and later) "Scalable Processor"
    -Server CPUs. It will be available in future non-server Intel parts
    -and future AMD processors.
    -
    -For anyone wishing to test or use this feature, it is available in
    -Amazon's EC2 C5 instances and is known to work there using an Ubuntu
    -17.04 image.
    -
    -Memory Protection Keys provides a mechanism for enforcing page-based
    -protections, but without requiring modification of the page tables
    -when an application changes protection domains. It works by
    -dedicating 4 previously ignored bits in each page table entry to a
    -"protection key", giving 16 possible keys.
    -
    -There is also a new user-accessible register (PKRU) with two separate
    -bits (Access Disable and Write Disable) for each key. Being a CPU
    -register, PKRU is inherently thread-local, potentially giving each
    +Memory Protection Keys provide a mechanism for enforcing page-based
    +protections, but without requiring modification of the page tables when an
    +application changes protection domains.
    +
    +Pkeys Userspace (PKU) is a feature which can be found on:
    + * Intel server CPUs, Skylake and later
    + * Intel client CPUs, Tiger Lake (11th Gen Core) and later
    + * Future AMD CPUs
    +
    +Pkeys work by dedicating 4 previously Reserved bits in each page table entry to
    +a "protection key", giving 16 possible keys.
    +
    +Protections for each key are defined with a per-CPU user-accessible register
    +(PKRU). Each of these is a 32-bit register storing two bits (Access Disable
    +and Write Disable) for each of 16 keys.
    +
    +Being a CPU register, PKRU is inherently thread-local, potentially giving each
    thread a different set of protections from every other thread.

    -There are two new instructions (RDPKRU/WRPKRU) for reading and writing
    -to the new register. The feature is only available in 64-bit mode,
    -even though there is theoretically space in the PAE PTEs. These
    -permissions are enforced on data access only and have no effect on
    -instruction fetches.
    +There are two instructions (RDPKRU/WRPKRU) for reading and writing to the
    +register. The feature is only available in 64-bit mode, even though there is
    +theoretically space in the PAE PTEs. These permissions are enforced on data
    +access only and have no effect on instruction fetches.

    Syscalls
    ========
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