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    Subject[PATCH 5.18 604/879] pinctrl: renesas: r8a779a0: Fix GPIO function on I2C-capable pins
    Date
    From: Geert Uytterhoeven <geert+renesas@glider.be>

    [ Upstream commit 4288caed9a6319b766dc0adf605c7b401180db34 ]

    Unlike on R-Car Gen3 SoCs, setting a bit to zero in a GPIO / Peripheral
    Function Select Register (GPSRn) on R-Car V3U is not always sufficient
    to configure a pin for GPIO. For I2C-capable pins, the I2C function
    must also be explicitly disabled in the corresponding Module Select
    Register (MODSELn).

    Add the missing FN_SEL_I2Ci_0 function enums to the pinmux_data[] array
    by temporarily overriding the GP_2_j_FN function enum to expand to two
    enums: the original GP_2_j_FN enum to configure the GSPR register bits,
    and the missing FN_SEL_I2Ci_0 enum to configure the MODSEL register
    bits.

    Fixes: 741a7370fc3b8b54 ("pinctrl: renesas: Initial R8A779A0 (V3U) PFC support")
    Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
    Link: https://lore.kernel.org/r/4611e29e7b105513883084c1d6dc39c3ac8b525c.1650610471.git.geert+renesas@glider.be
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/pinctrl/renesas/pfc-r8a779a0.c | 29 ++++++++++++++++++++++++++
    1 file changed, 29 insertions(+)

    diff --git a/drivers/pinctrl/renesas/pfc-r8a779a0.c b/drivers/pinctrl/renesas/pfc-r8a779a0.c
    index 4a668a04b7ca..0c26e95ba7db 100644
    --- a/drivers/pinctrl/renesas/pfc-r8a779a0.c
    +++ b/drivers/pinctrl/renesas/pfc-r8a779a0.c
    @@ -629,7 +629,36 @@ enum {
    };

    static const u16 pinmux_data[] = {
    +/* Using GP_2_[2-15] requires disabling I2C in MOD_SEL2 */
    +#define GP_2_2_FN GP_2_2_FN, FN_SEL_I2C0_0
    +#define GP_2_3_FN GP_2_3_FN, FN_SEL_I2C0_0
    +#define GP_2_4_FN GP_2_4_FN, FN_SEL_I2C1_0
    +#define GP_2_5_FN GP_2_5_FN, FN_SEL_I2C1_0
    +#define GP_2_6_FN GP_2_6_FN, FN_SEL_I2C2_0
    +#define GP_2_7_FN GP_2_7_FN, FN_SEL_I2C2_0
    +#define GP_2_8_FN GP_2_8_FN, FN_SEL_I2C3_0
    +#define GP_2_9_FN GP_2_9_FN, FN_SEL_I2C3_0
    +#define GP_2_10_FN GP_2_10_FN, FN_SEL_I2C4_0
    +#define GP_2_11_FN GP_2_11_FN, FN_SEL_I2C4_0
    +#define GP_2_12_FN GP_2_12_FN, FN_SEL_I2C5_0
    +#define GP_2_13_FN GP_2_13_FN, FN_SEL_I2C5_0
    +#define GP_2_14_FN GP_2_14_FN, FN_SEL_I2C6_0
    +#define GP_2_15_FN GP_2_15_FN, FN_SEL_I2C6_0
    PINMUX_DATA_GP_ALL(),
    +#undef GP_2_2_FN
    +#undef GP_2_3_FN
    +#undef GP_2_4_FN
    +#undef GP_2_5_FN
    +#undef GP_2_6_FN
    +#undef GP_2_7_FN
    +#undef GP_2_8_FN
    +#undef GP_2_9_FN
    +#undef GP_2_10_FN
    +#undef GP_2_11_FN
    +#undef GP_2_12_FN
    +#undef GP_2_13_FN
    +#undef GP_2_14_FN
    +#undef GP_2_15_FN

    PINMUX_SINGLE(MMC_D7),
    PINMUX_SINGLE(MMC_D6),
    --
    2.35.1


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