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    Subject[PATCH 5.17 296/772] spi: rockchip: fix missing error on unsupported SPI_CS_HIGH
    Date
    From: Luca Ceresoli <luca.ceresoli@bootlin.com>

    [ Upstream commit d5d933f09ac326aebad85bfb787cc786ad477711 ]

    The hardware (except for the ROCKCHIP_SPI_VER2_TYPE2 version) does not
    support active-high native chip selects. However if such a CS is configured
    the core does not error as it normally should, because the
    'ctlr->use_gpio_descriptors = true' line in rockchip_spi_probe() makes the
    core set SPI_CS_HIGH in ctlr->mode_bits.

    In such a case the spi-rockchip driver operates normally but produces an
    active-low chip select signal without notice.

    There is no provision in the current core code to handle this
    situation. Fix by adding a check in the ctlr->setup function (similarly to
    what spi-atmel.c does).

    This cannot be done reading the SPI_CS_HIGH but in ctlr->mode_bits because
    that bit gets always set by the core for master mode (see above).

    Fixes: eb1262e3cc8b ("spi: spi-rockchip: use num-cs property and ctlr->enable_gpiods")
    Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
    Link: https://lore.kernel.org/r/20220421213251.1077899-1-luca.ceresoli@bootlin.com
    Signed-off-by: Mark Brown <broonie@kernel.org>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/spi/spi-rockchip.c | 8 ++++++++
    1 file changed, 8 insertions(+)

    diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c
    index 83da8fdb3c02..b721b62118e1 100644
    --- a/drivers/spi/spi-rockchip.c
    +++ b/drivers/spi/spi-rockchip.c
    @@ -196,6 +196,8 @@ struct rockchip_spi {

    bool slave_abort;
    bool cs_inactive; /* spi slave tansmition stop when cs inactive */
    + bool cs_high_supported; /* native CS supports active-high polarity */
    +
    struct spi_transfer *xfer; /* Store xfer temporarily */
    };

    @@ -718,6 +720,11 @@ static int rockchip_spi_setup(struct spi_device *spi)
    struct rockchip_spi *rs = spi_controller_get_devdata(spi->controller);
    u32 cr0;

    + if (!spi->cs_gpiod && (spi->mode & SPI_CS_HIGH) && !rs->cs_high_supported) {
    + dev_warn(&spi->dev, "setup: non GPIO CS can't be active-high\n");
    + return -EINVAL;
    + }
    +
    pm_runtime_get_sync(rs->dev);

    cr0 = readl_relaxed(rs->regs + ROCKCHIP_SPI_CTRLR0);
    @@ -898,6 +905,7 @@ static int rockchip_spi_probe(struct platform_device *pdev)

    switch (readl_relaxed(rs->regs + ROCKCHIP_SPI_VERSION)) {
    case ROCKCHIP_SPI_VER2_TYPE2:
    + rs->cs_high_supported = true;
    ctlr->mode_bits |= SPI_CS_HIGH;
    if (ctlr->can_dma && slave_mode)
    rs->cs_inactive = true;
    --
    2.35.1


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