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    Subject[PATCH 5.17 236/772] drm: bridge: icn6211: Fix HFP_HSW_HBP_HI and HFP_MIN handling
    Date
    From: Marek Vasut <marex@denx.de>

    [ Upstream commit c0ff7a649d62105a9308cc3ac36e52a4669d9cb4 ]

    The HFP_HSW_HBP_HI register must be programmed with 2 LSbits of each
    Horizontal Front Porch/Sync/Back Porch. Currently the driver programs
    this register to 0, which breaks displays with either value above 255.

    The HFP_MIN register must be set to the same value as HFP_LI, otherwise
    there is visible image distortion, usually in the form of missing lines
    at the bottom of the panel.

    Fix this by correctly programming the HFP_HSW_HBP_HI and HFP_MIN registers.

    Acked-by: Maxime Ripard <maxime@cerno.tech>
    Fixes: ce517f18944e3 ("drm: bridge: Add Chipone ICN6211 MIPI-DSI to RGB bridge")
    Signed-off-by: Marek Vasut <marex@denx.de>
    Cc: Jagan Teki <jagan@amarulasolutions.com>
    Cc: Maxime Ripard <maxime@cerno.tech>
    Cc: Robert Foss <robert.foss@linaro.org>
    Cc: Sam Ravnborg <sam@ravnborg.org>
    Cc: Thomas Zimmermann <tzimmermann@suse.de>
    To: dri-devel@lists.freedesktop.org
    Signed-off-by: Robert Foss <robert.foss@linaro.org>
    Link: https://patchwork.freedesktop.org/patch/msgid/20220331150509.9838-3-marex@denx.de
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/gpu/drm/bridge/chipone-icn6211.c | 23 ++++++++++++++++-------
    1 file changed, 16 insertions(+), 7 deletions(-)

    diff --git a/drivers/gpu/drm/bridge/chipone-icn6211.c b/drivers/gpu/drm/bridge/chipone-icn6211.c
    index eb26615b2993..d7eedf35e841 100644
    --- a/drivers/gpu/drm/bridge/chipone-icn6211.c
    +++ b/drivers/gpu/drm/bridge/chipone-icn6211.c
    @@ -34,6 +34,9 @@
    #define HSYNC_LI 0x24
    #define HBP_LI 0x25
    #define HFP_HSW_HBP_HI 0x26
    +#define HFP_HSW_HBP_HI_HFP(n) (((n) & 0x300) >> 4)
    +#define HFP_HSW_HBP_HI_HS(n) (((n) & 0x300) >> 6)
    +#define HFP_HSW_HBP_HI_HBP(n) (((n) & 0x300) >> 8)
    #define VFP 0x27
    #define VSYNC 0x28
    #define VBP 0x29
    @@ -165,6 +168,7 @@ static void chipone_enable(struct drm_bridge *bridge)
    {
    struct chipone *icn = bridge_to_chipone(bridge);
    struct drm_display_mode *mode = bridge_to_mode(bridge);
    + u16 hfp, hbp, hsync;

    ICN6211_DSI(icn, MIPI_CFG_PW, MIPI_CFG_PW_CONFIG_DSI);

    @@ -180,13 +184,18 @@ static void chipone_enable(struct drm_bridge *bridge)
    ((mode->hdisplay >> 8) & 0xf) |
    (((mode->vdisplay >> 8) & 0xf) << 4));

    - ICN6211_DSI(icn, HFP_LI, mode->hsync_start - mode->hdisplay);
    + hfp = mode->hsync_start - mode->hdisplay;
    + hsync = mode->hsync_end - mode->hsync_start;
    + hbp = mode->htotal - mode->hsync_end;

    - ICN6211_DSI(icn, HSYNC_LI, mode->hsync_end - mode->hsync_start);
    -
    - ICN6211_DSI(icn, HBP_LI, mode->htotal - mode->hsync_end);
    -
    - ICN6211_DSI(icn, HFP_HSW_HBP_HI, 0x00);
    + ICN6211_DSI(icn, HFP_LI, hfp & 0xff);
    + ICN6211_DSI(icn, HSYNC_LI, hsync & 0xff);
    + ICN6211_DSI(icn, HBP_LI, hbp & 0xff);
    + /* Top two bits of Horizontal Front porch/Sync/Back porch */
    + ICN6211_DSI(icn, HFP_HSW_HBP_HI,
    + HFP_HSW_HBP_HI_HFP(hfp) |
    + HFP_HSW_HBP_HI_HS(hsync) |
    + HFP_HSW_HBP_HI_HBP(hbp));

    ICN6211_DSI(icn, VFP, mode->vsync_start - mode->vdisplay);

    @@ -196,7 +205,7 @@ static void chipone_enable(struct drm_bridge *bridge)

    /* dsi specific sequence */
    ICN6211_DSI(icn, SYNC_EVENT_DLY, 0x80);
    - ICN6211_DSI(icn, HFP_MIN, 0x28);
    + ICN6211_DSI(icn, HFP_MIN, hfp & 0xff);
    ICN6211_DSI(icn, MIPI_PD_CK_LANE, 0xa0);
    ICN6211_DSI(icn, PLL_CTRL(12), 0xff);
    ICN6211_DSI(icn, BIST_POL, BIST_POL_DE_POL);
    --
    2.35.1


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