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    Subject[PATCH 5.15 467/667] powerpc/xive: Add some error handling code to xive_spapr_init()
    Date
    From: Christophe JAILLET <christophe.jaillet@wanadoo.fr>

    [ Upstream commit e414e2938ee26e734f19e92a60cd090ebaff37e6 ]

    'xive_irq_bitmap_add()' can return -ENOMEM.
    In this case, we should free the memory already allocated and return
    'false' to the caller.

    Also add an error path which undoes the 'tima = ioremap(...)'

    Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
    Reviewed-by: Cédric Le Goater <clg@kaod.org>
    Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
    Link: https://lore.kernel.org/r/564998101804886b151235c8a9f93020923bfd2c.1643718324.git.christophe.jaillet@wanadoo.fr
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    arch/powerpc/sysdev/xive/spapr.c | 36 +++++++++++++++++++++++++-------
    1 file changed, 28 insertions(+), 8 deletions(-)

    diff --git a/arch/powerpc/sysdev/xive/spapr.c b/arch/powerpc/sysdev/xive/spapr.c
    index 1179632560b8..905dd40bd5cd 100644
    --- a/arch/powerpc/sysdev/xive/spapr.c
    +++ b/arch/powerpc/sysdev/xive/spapr.c
    @@ -67,6 +67,17 @@ static int xive_irq_bitmap_add(int base, int count)
    return 0;
    }

    +static void xive_irq_bitmap_remove_all(void)
    +{
    + struct xive_irq_bitmap *xibm, *tmp;
    +
    + list_for_each_entry_safe(xibm, tmp, &xive_irq_bitmaps, list) {
    + list_del(&xibm->list);
    + kfree(xibm->bitmap);
    + kfree(xibm);
    + }
    +}
    +
    static int __xive_irq_bitmap_alloc(struct xive_irq_bitmap *xibm)
    {
    int irq;
    @@ -803,7 +814,7 @@ bool __init xive_spapr_init(void)
    u32 val;
    u32 len;
    const __be32 *reg;
    - int i;
    + int i, err;

    if (xive_spapr_disabled())
    return false;
    @@ -828,23 +839,26 @@ bool __init xive_spapr_init(void)
    }

    if (!xive_get_max_prio(&max_prio))
    - return false;
    + goto err_unmap;

    /* Feed the IRQ number allocator with the ranges given in the DT */
    reg = of_get_property(np, "ibm,xive-lisn-ranges", &len);
    if (!reg) {
    pr_err("Failed to read 'ibm,xive-lisn-ranges' property\n");
    - return false;
    + goto err_unmap;
    }

    if (len % (2 * sizeof(u32)) != 0) {
    pr_err("invalid 'ibm,xive-lisn-ranges' property\n");
    - return false;
    + goto err_unmap;
    }

    - for (i = 0; i < len / (2 * sizeof(u32)); i++, reg += 2)
    - xive_irq_bitmap_add(be32_to_cpu(reg[0]),
    - be32_to_cpu(reg[1]));
    + for (i = 0; i < len / (2 * sizeof(u32)); i++, reg += 2) {
    + err = xive_irq_bitmap_add(be32_to_cpu(reg[0]),
    + be32_to_cpu(reg[1]));
    + if (err < 0)
    + goto err_mem_free;
    + }

    /* Iterate the EQ sizes and pick one */
    of_property_for_each_u32(np, "ibm,xive-eq-sizes", prop, reg, val) {
    @@ -855,10 +869,16 @@ bool __init xive_spapr_init(void)

    /* Initialize XIVE core with our backend */
    if (!xive_core_init(np, &xive_spapr_ops, tima, TM_QW1_OS, max_prio))
    - return false;
    + goto err_mem_free;

    pr_info("Using %dkB queues\n", 1 << (xive_queue_shift - 10));
    return true;
    +
    +err_mem_free:
    + xive_irq_bitmap_remove_all();
    +err_unmap:
    + iounmap(tima);
    + return false;
    }

    machine_arch_initcall(pseries, xive_core_debug_init);
    --
    2.35.1


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