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    Subject[PATCH 5.15 054/667] x86/platform/uv: Update TSC sync state for UV5
    Date
    From: Mike Travis <mike.travis@hpe.com>

    [ Upstream commit bb3ab81bdbd53f88f26ffabc9fb15bd8466486ec ]

    The UV5 platform synchronizes the TSCs among all chassis, and will not
    proceed to OS boot without achieving synchronization. Previous UV
    platforms provided a register indicating successful synchronization.
    This is no longer available on UV5. On this platform TSC_ADJUST
    should not be reset by the kernel.

    Signed-off-by: Mike Travis <mike.travis@hpe.com>
    Signed-off-by: Steve Wahl <steve.wahl@hpe.com>
    Signed-off-by: Borislav Petkov <bp@suse.de>
    Reviewed-by: Dimitri Sivanich <dimitri.sivanich@hpe.com>
    Acked-by: Thomas Gleixner <tglx@linutronix.de>
    Link: https://lore.kernel.org/r/20220406195149.228164-3-steve.wahl@hpe.com
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    arch/x86/kernel/apic/x2apic_uv_x.c | 8 +++++++-
    1 file changed, 7 insertions(+), 1 deletion(-)

    diff --git a/arch/x86/kernel/apic/x2apic_uv_x.c b/arch/x86/kernel/apic/x2apic_uv_x.c
    index f5a48e66e4f5..a6e9c2794ef5 100644
    --- a/arch/x86/kernel/apic/x2apic_uv_x.c
    +++ b/arch/x86/kernel/apic/x2apic_uv_x.c
    @@ -199,7 +199,13 @@ static void __init uv_tsc_check_sync(void)
    int mmr_shift;
    char *state;

    - /* Different returns from different UV BIOS versions */
    + /* UV5 guarantees synced TSCs; do not zero TSC_ADJUST */
    + if (!is_uv(UV2|UV3|UV4)) {
    + mark_tsc_async_resets("UV5+");
    + return;
    + }
    +
    + /* UV2,3,4, UV BIOS TSC sync state available */
    mmr = uv_early_read_mmr(UVH_TSC_SYNC_MMR);
    mmr_shift =
    is_uv2_hub() ? UVH_TSC_SYNC_SHIFT_UV2K : UVH_TSC_SYNC_SHIFT;
    --
    2.35.1


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