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SubjectRe: [PATCH v2 06/12] irqchip: mips-gic: Multi-cluster support
On Wed, 25 May 2022 13:10:24 +0100,
Dragan Mladjenovic <> wrote:
> From: Paul Burton <>
> The MIPS I6500 CPU & CM (Coherence Manager) 3.5 introduce the concept of
> multiple clusters to the system. In these systems each cluster contains
> its own GIC, so the GIC isn't truly global any longer. We do have the
> ability to access registers in the GICs of remote clusters using a
> redirect register block much like the redirect register blocks provided
> by the CM & CPC, and configured through the same GCR_REDIRECT register
> that we our mips_cm_lock_other() abstraction builds upon.
> It is expected that external interrupts are connected identically to all
> clusters. That is, if we have a device providing an interrupt connected
> to GIC interrupt pin 0 then it should be connected to pin 0 of every GIC
> in the system. This simplifies things somewhat by allowing us for the
> most part to treat the GIC as though it is still truly global, so long
> as we take care to configure interrupts in the cluster that we want them
> affine to.

I can see how this can work for level interrupts, but how does this
work for edge interrupts? Is there any guarantee that the interrupt
will be discarded if routed to a cluster where it isn't configured?

Otherwise, I can imagine plenty of spurious interrupts on affinity



Without deviation from the norm, progress is not possible.

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