Messages in this thread | | | From | kah.jing.lee@intel ... | Subject | Re: [PATCH 1/2] drivers: misc: intel_sysid: Add sysid from arch to drivers | Date | Fri, 3 Jun 2022 12:57:33 +0800 |
| |
From: Kah Jing Lee <kah.jing.lee@intel.com>
> On Thu, Jun 02, 2022 at 08:22:13PM +0800, kah.jing.lee@intel.com wrote: > > From: Kah Jing Lee <kah.jing.lee@intel.com> > > > > Add sysid driver. The Altera(Intel) Sysid component is generally part of an > > FPGA design. The component can be hotplugged when the FPGA is reconfigured. > > This patch fixes the driver to support the component being hotplugged. > > > > Usage: > > cat /sys/bus/platform/devices/soc:base_fpga_region/ > > soc:base_fpga_region:fpga_pr_region0/[addr.sysid]/sysid/id > > cat /sys/bus/platform/devices/soc:base_fpga_region/ > > soc:base_fpga_region:fpga_pr_region0/[addr.sysid]/sysid/timestamp > > > > Signed-off-by: Ley Foon Tan <lftan@altera.com> > > Signed-off-by: Kah Jing Lee <kah.jing.lee@intel.com> > > Please work with the Intel open source group as there are some internal > Intel requirements that you have not met here in order to be able to > submit a patch for external people to review. I'll refrain from > reviewing or even considering this to be able to be accepted this until > that happens.
Will update the license header and commit message, and resent. Thanks for pointing out =).
> good luck! > > greg k-h
| |