Messages in this thread | | | Date | Wed, 29 Jun 2022 17:26:25 +0100 | From | Marc Zyngier <> | Subject | Re: [PATCH v6 5/5] pinctrl: renesas: pinctrl-rzg2l: Add IRQ domain to handle GPIO interrupt |
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On Sat, 25 Jun 2022 21:06:00 +0100, Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > > Add IRQ domain to RZ/G2L pinctrl driver to handle GPIO interrupt. > > GPIO0-GPIO122 pins can be used as IRQ lines but only 32 pins can be > used as IRQ lines at a given time. Selection of pins as IRQ lines > is handled by IA55 (which is the IRQC block) which sits in between the > GPIO and GIC. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > --- > drivers/pinctrl/renesas/pinctrl-rzg2l.c | 236 ++++++++++++++++++++++++ > 1 file changed, 236 insertions(+) >
[...]
> +static void *rzg2l_gpio_populate_parent_fwspec(struct gpio_chip *chip, > + unsigned int parent_hwirq, > + unsigned int parent_type) > +{ > + struct irq_fwspec *fwspec; > + > + fwspec = kzalloc(sizeof(*fwspec), GFP_KERNEL); > + if (!fwspec) > + return NULL; > + > + fwspec->fwnode = chip->irq.parent_domain->fwnode; > + fwspec->param_count = 2; > + fwspec->param[0] = parent_hwirq; > + fwspec->param[1] = parent_type; > + > + return fwspec; > +}
I jumped at this one again.
Can you please pick [1] as part of your series and write this in a way that doesn't require extra memory allocation? It has already been ack'ed by Linus anyway, and we'd put an end to this thing for good.
Thanks,
M.
[1] https://lore.kernel.org/r/20220512162320.2213488-1-maz@kernel.org
-- Without deviation from the norm, progress is not possible.
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