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    SubjectRe: [PATCH v12 05/10] drm/mediatek: Add MT8195 Embedded DisplayPort driver
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    Hi, Bo-Chen:

    On Mon, 2022-06-27 at 16:03 +0800, Bo-Chen Chen wrote:
    > From: Markus Schneider-Pargmann <msp@baylibre.com>
    >
    > This patch adds a embedded displayport driver for the MediaTek mt8195
    > SoC.
    >
    > It supports the MT8195, the embedded DisplayPort units. It offers
    > DisplayPort 1.4 with up to 4 lanes.
    >
    > The driver creates a child device for the phy. The child device will
    > never exist without the parent being active. As they are sharing a
    > register range, the parent passes a regmap pointer to the child so
    > that
    > both can work with the same register range. The phy driver sets
    > device
    > data that is read by the parent to get the phy device that can be
    > used
    > to control the phy properties.
    >
    > This driver is based on an initial version by
    > Jitao shi <jitao.shi@mediatek.com>
    >
    > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
    > Signed-off-by: Guillaume Ranquet <granquet@baylibre.com>
    > [Bo-Chen: Cleanup the drivers and modify comments from reviewers]
    > Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
    > ---

    [snip]

    > +++ b/drivers/gpu/drm/mediatek/mtk_dp_reg.h
    > @@ -0,0 +1,543 @@
    > +/* SPDX-License-Identifier: GPL-2.0 */
    > +/*
    > + * Copyright (c) 2019-2022 MediaTek Inc.
    > + * Copyright (c) 2022 BayLibre
    > + */
    > +#ifndef _MTK_DP_REG_H_
    > +#define _MTK_DP_REG_H_
    > +
    > +#define TOP_OFFSET 0x2000
    > +#define ENC0_OFFSET 0x3000
    > +#define ENC1_OFFSET 0x3200
    > +#define TRANS_OFFSET 0x3400
    > +#define AUX_OFFSET 0x3600
    > +#define SEC_OFFSET 0x4000
    > +
    > +#define MTK_DP_SIP_ATF_VIDEO_UNMUTE BIT(5)

    Useless, so remove it.

    Regards,
    CK

    > +#define MTK_DP_SIP_ATF_EDP_VIDEO_UNMUTE (BIT(0) | BIT(5))
    > +

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