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    SubjectRe: [PATCH v1 11/11] mfd: intel_soc_pmic_bxtwc: Fix spelling in the comment
    On Tue, Jun 28, 2022 at 10:56:31AM +0100, Lee Jones wrote:
    > On Tue, 28 Jun 2022, Andy Shevchenko wrote:
    > > On Mon, Jun 27, 2022 at 10:33:17AM +0100, Lee Jones wrote:
    > > > On Thu, 16 Jun 2022, Andy Shevchenko wrote:
    > >
    > > > > - * There is known hw bug. Upon reset BIT 5 of register
    > > > > + * There is known HW bug. Upon reset BIT 5 of register
    > > >
    > > > You may as well fix the grammar while you're at it.
    > >
    > > Any suggestion from a native speaker? I can propose a few changes, but I'm
    > > totally unsure.
    >
    > No massive changes, just:
    >
    > * There is a known H/W bug. Upon reset, BIT 5 of register
    > - --- -
    >
    > > > > * BXTWC_CHGR_LVL1_IRQ is 0 which is the expected value. However,
    > > > > * later it's set to 1(masked) automatically by hardware. So we
    > > > > - * have the software workaround here to unmaksed it in order to let
    > > > > - * charger interrutp work.
    > > > > + * have the software workaround here to unmasked it in order to let
    > > > > + * charger interrupt work.
    >
    > * place a software workaround here to unmask it again in order to re-enable
    > ------- ------ ----- ---------
    >
    > * the charger interrupt.
    > ---
    >
    > Something like that. Feel free to adapt it further as you see fit.

    Thank you, Lee, I will do as suggested!

    --
    With Best Regards,
    Andy Shevchenko


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