Messages in this thread | | | From | Geert Uytterhoeven <> | Date | Tue, 28 Jun 2022 11:48:41 +0200 | Subject | Re: [PATCH 1/2] dt-bindings: clock: r9a07g043-cpg: Add Renesas RZ/Five CPG Clock and Reset Definitions |
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On Wed, Jun 22, 2022 at 8:17 PM Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > Renesas RZ/Five SoC has almost the same clock structure compared to the > Renesas RZ/G2UL SoC, re-use the r9a07g043-cpg.h header file and just > amend the RZ/Five CPG clock and reset definitions. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Will queue in renesas-clk-for-v5.20.
Gr{oetje,eeting}s,
Geert
-- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
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