lkml.org 
[lkml]   [2022]   [Jun]   [28]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    /
    Date
    From
    SubjectRe: [PATCH v2 3/3] fpga: zynqmp-fpga: Adds status interface
    On Tue, Jun 21, 2022 at 02:58:33PM +0530, Nava kishore Manne wrote:
    > Adds status interface for zynqmp-fpga, It's a read only
    > interface which allows the user to get the PL status.
    >
    > Usage:
    > To read the PL configuration status
    > cat /sys/class/fpga_manager/<fpga>/status
    >
    > Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
    > ---
    > Changes for v2:
    > - Updated status messages handling logic as suggested by Xu Yilun.
    >
    > drivers/fpga/zynqmp-fpga.c | 53 ++++++++++++++++++++++++++++++++++++++
    > 1 file changed, 53 insertions(+)
    >
    > diff --git a/drivers/fpga/zynqmp-fpga.c b/drivers/fpga/zynqmp-fpga.c
    > index c60f20949c47..e194bba91d3f 100644
    > --- a/drivers/fpga/zynqmp-fpga.c
    > +++ b/drivers/fpga/zynqmp-fpga.c
    > @@ -14,6 +14,19 @@
    >
    > /* Constant Definitions */
    > #define IXR_FPGA_DONE_MASK BIT(3)
    > +#define READ_DMA_SIZE 256U
    > +
    > +/* Error Register */
    > +#define IXR_FPGA_ERR_CRC_ERR BIT(0)
    > +#define IXR_FPGA_ERR_SECURITY_ERR BIT(16)
    > +
    > +/* Signal Status Register. For details refer ug570 */
    > +#define IXR_FPGA_END_OF_STARTUP BIT(4)
    > +#define IXR_FPGA_GST_CFG_B BIT(5)
    > +#define IXR_FPGA_INIT_B_INTERNAL BIT(11)
    > +#define IXR_FPGA_DONE_INTERNAL_SIGNAL BIT(13)
    > +
    > +#define IXR_FPGA_CONFIG_STAT_OFFSET 7U
    >
    > /**
    > * struct zynqmp_fpga_priv - Private data structure
    > @@ -77,8 +90,48 @@ static enum fpga_mgr_states zynqmp_fpga_ops_state(struct fpga_manager *mgr)
    > return FPGA_MGR_STATE_UNKNOWN;
    > }
    >
    > +static ssize_t zynqmp_fpga_ops_status(struct fpga_manager *mgr, char *buf)
    > +{
    > + unsigned int *kbuf, reg_val;
    > + dma_addr_t dma_addr;
    > + ssize_t len = 0;
    > + int ret;
    > +
    > + kbuf = dma_alloc_coherent(mgr->dev.parent, READ_DMA_SIZE,
    > + &dma_addr, GFP_KERNEL);
    > + if (!kbuf)
    > + return -ENOMEM;
    > +
    > + ret = zynqmp_pm_fpga_read(IXR_FPGA_CONFIG_STAT_OFFSET, dma_addr,
    > + PM_FPGA_READ_CONFIG_REG, &reg_val);
    > + if (ret) {
    > + len += sprintf(buf + len, "firmware error\n");
    > + goto free_dmabuf;
    > + }
    > +
    > + if (reg_val & IXR_FPGA_ERR_CRC_ERR)
    > + len += sprintf(buf + len, "reconfig CRC error\n");
    > + if (reg_val & IXR_FPGA_ERR_SECURITY_ERR)
    > + len += sprintf(buf + len, "reconfig security error\n");
    > + if (!(reg_val & IXR_FPGA_INIT_B_INTERNAL))
    > + len += sprintf(buf + len, "Device Initialization error\n");
    > + if (!(reg_val & IXR_FPGA_DONE_INTERNAL_SIGNAL))
    > + len += sprintf(buf + len, "Device internal signal error\n");
    > + if (!(reg_val & IXR_FPGA_GST_CFG_B))
    > + len += sprintf(buf + len,
    > + "All I/Os are placed in High-Z state\n");
    > + if (!(reg_val & IXR_FPGA_END_OF_STARTUP))
    > + len += sprintf(buf + len, "Device sequence error\n");

    Expressing multiple lines of data is discouraged, one value or an array
    of values is OK. For more details, see
    Documentation/filesystems/sysfs.rst

    Thanks,
    Yilun

    > +
    > +free_dmabuf:
    > + dma_free_coherent(mgr->dev.parent, READ_DMA_SIZE, buf, dma_addr);
    > +
    > + return len;
    > +}
    > +
    > static const struct fpga_manager_ops zynqmp_fpga_ops = {
    > .state = zynqmp_fpga_ops_state,
    > + .status = zynqmp_fpga_ops_status,
    > .write_init = zynqmp_fpga_ops_write_init,
    > .write = zynqmp_fpga_ops_write,
    > };
    > --
    > 2.25.1

    \
     
     \ /
      Last update: 2022-06-28 10:49    [W:3.705 / U:0.188 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site