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SubjectRE: [PATCH v2 1/2] mtd: rawnand: arasan: Update NAND bus clock instead of system clock
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Hello Miquel,

> -----Original Message-----
> From: Miquel Raynal <miquel.raynal@bootlin.com>
> Sent: Saturday, June 25, 2022 12:15 AM
> To: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com>
> Cc: vigneshr@ti.com; git (AMD-Xilinx) <git@amd.com>;
> boris.brezillon@collabora.com; linux-mtd@lists.infradead.org; linux-
> kernel@vger.kernel.org; Mahapatra, Amit Kumar <amit.kumar-
> mahapatra@amd.com>; Mahapatra, Amit Kumar <amit.kumar-
> mahapatra@amd.com>
> Subject: Re: [PATCH v2 1/2] mtd: rawnand: arasan: Update NAND bus clock
> instead of system clock
>
> Hi Amit,
>
> amit.kumar-mahapatra@xilinx.com wrote on Tue, 21 Jun 2022 14:24:59
> +0530:
>
> > In current implementation the Arasan NAND driver is updating the
> > system clock(i.e., anand->clk) in accordance to the timing modes
> > (i.e., SDR or NVDDR). But as per the Arasan NAND controller spec the
> > flash clock or the NAND bus clock(i.e., nfc->bus_clk), need to be
> > updated instead. This patch keeps the system clock unchanged and
> > updates the NAND bus clock as per the timing modes.
>
> This is not what you do below. If the clock that is changed is the wrong one,
> then just change the clock used in the clk_set_rate call instead of calling
> clk_set_rate twice at the wrong location.
> ->set_interface is done once per chip, if you have two different chips
> on the same system you must change the clock when you switch from one
> chip to the other. Your current implementation disrespects that,
> unfortunately.


Will make the changes in the next iteration.
>
> >
> > Fixes: 197b88fecc50 ("mtd: rawnand: arasan: Add new Arasan NAND
> > controller")
>
> Requires a Cc: stable tag

Will this in the next iteration.

Regards,
Amit
>
> > Signed-off-by: Amit Kumar Mahapatra <amit.kumar-
> mahapatra@xilinx.com>
> > ---
> > drivers/mtd/nand/raw/arasan-nand-controller.c | 16 +++++++++++++---
> > 1 file changed, 13 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/mtd/nand/raw/arasan-nand-controller.c
> > b/drivers/mtd/nand/raw/arasan-nand-controller.c
> > index 53bd10738418..4f6da82dd2b1 100644
> > --- a/drivers/mtd/nand/raw/arasan-nand-controller.c
> > +++ b/drivers/mtd/nand/raw/arasan-nand-controller.c
> > @@ -968,6 +968,7 @@ static int anfc_setup_interface(struct nand_chip
> *chip, int target,
> > const struct nand_sdr_timings *sdr;
> > const struct nand_nvddr_timings *nvddr;
> > unsigned int tccs_min, dqs_mode, fast_tcad;
> > + int ret;
> >
> > if (nand_interface_is_nvddr(conf)) {
> > nvddr = nand_get_nvddr_timings(conf); @@ -1043,7
> +1044,11 @@ static
> > int anfc_setup_interface(struct nand_chip *chip, int target,
> > DQS_BUFF_SEL_OUT(dqs_mode);
> > }
> >
> > - anand->clk = ANFC_XLNX_SDR_DFLT_CORE_CLK;
> > + ret = clk_set_rate(nfc->bus_clk, ANFC_XLNX_SDR_DFLT_CORE_CLK);
> > + if (ret) {
> > + dev_err(nfc->dev, "Failed to change bus clock rate\n");
> > + return ret;
> > + }
> >
> > /*
> > * Due to a hardware bug in the ZynqMP SoC, SDR timing modes 0-1
> > work @@ -1052,8 +1057,13 @@ static int anfc_setup_interface(struct
> nand_chip *chip, int target,
> > * 80MHz when using SDR modes 2-5 with this SoC.
> > */
> > if (of_device_is_compatible(np, "xlnx,zynqmp-nand-controller") &&
> > - nand_interface_is_sdr(conf) && conf->timings.mode >= 2)
> > - anand->clk = ANFC_XLNX_SDR_HS_CORE_CLK;
> > + nand_interface_is_sdr(conf) && conf->timings.mode >= 2) {
> > + ret = clk_set_rate(nfc->bus_clk,
> ANFC_XLNX_SDR_HS_CORE_CLK);
> > + if (ret) {
> > + dev_err(nfc->dev, "Failed to change bus clock
> rate\n");
> > + return ret;
> > + }
> > + }
> >
> > return 0;
> > }
>
>
> Thanks,
> Miquèl
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