Messages in this thread | | | Date | Mon, 27 Jun 2022 09:01:01 +0200 | Subject | Re: [PATCH v3 6/6] drm/meson: add support for MIPI-DSI transceiver | From | Neil Armstrong <> |
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Hi,
On 27/06/2022 00:32, Martin Blumenstingl wrote: > Hi Neil, > > On Fri, Jun 17, 2022 at 9:27 AM Neil Armstrong <narmstrong@baylibre.com> wrote: >> +/* [31:16] RW intr_stat/clr. Default 0. >> + * For each bit, read as this interrupt level status, >> + * write 1 to clear. > Do you know if an interrupt line from GIC is routed to the MIPI-DSI > transceiver? If so, we should make it mandatory in patch #1 of this > series (dt-bindings patch), even though it's not in use by the driver > at the moment.
Probably yes, let me check
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